AU4749279A - Time signal recovery during digital signal transmission - Google Patents

Time signal recovery during digital signal transmission

Info

Publication number
AU4749279A
AU4749279A AU47492/79A AU4749279A AU4749279A AU 4749279 A AU4749279 A AU 4749279A AU 47492/79 A AU47492/79 A AU 47492/79A AU 4749279 A AU4749279 A AU 4749279A AU 4749279 A AU4749279 A AU 4749279A
Authority
AU
Australia
Prior art keywords
signal
voltage
input
output
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU47492/79A
Other versions
AU526026B2 (en
Inventor
Otmar Ringelhaan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of AU4749279A publication Critical patent/AU4749279A/en
Application granted granted Critical
Publication of AU526026B2 publication Critical patent/AU526026B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Dc Digital Transmission (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
  • Forging (AREA)
  • Investigation Of Foundation Soil And Reinforcement Of Foundation Soil By Compacting Or Drainage (AREA)

Abstract

1. Arrangement for the clock signal recovery in the digital signal transmission comprising a phase discriminator (PD) which contains a control input (E) for the input signal and whose signal output (SA) is connected to the control input (RE1) of the first voltage-controlled oscillator (VCO1) by means of a first loop filter (LF1), characterized in that in the case of digital signals in the RZ-form the output of the first voltage-controlled oscillator (VCO1) is connected both to the signal input (SE) of the phase discriminator and to the signal input of a frequency-phase comparator (FPD), that the signal output of this frequency-phase comparator (FPD) is connected to the control input (RE2) of a second voltage-controlled oscillator (VCO2) by means of a second loop filter (LF2), and that the output of the second voltage-controlled oscillator is connected both to the clock signal input (VI) of frequency phase comparator (FPD) and to the output terminal (A) of the arrangement.
AU47492/79A 1978-05-29 1979-05-28 Time signal recovery during digital signal transmission Ceased AU526026B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2823343A DE2823343B1 (en) 1978-05-29 1978-05-29 Method and arrangement for clock signal recovery in digital signal transmission
DE28233434 1978-05-29

Publications (2)

Publication Number Publication Date
AU4749279A true AU4749279A (en) 1979-12-06
AU526026B2 AU526026B2 (en) 1982-12-16

Family

ID=6040426

Family Applications (1)

Application Number Title Priority Date Filing Date
AU47492/79A Ceased AU526026B2 (en) 1978-05-29 1979-05-28 Time signal recovery during digital signal transmission

Country Status (7)

Country Link
EP (1) EP0006988B1 (en)
JP (1) JPS54161812A (en)
AT (1) ATE1081T1 (en)
AU (1) AU526026B2 (en)
BR (1) BR7903319A (en)
DE (2) DE2823343B1 (en)
DK (1) DK219379A (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4356518A (en) * 1980-02-01 1982-10-26 Ampex Corporation High frequency digital PCM decoding apparatus
JPS5933950A (en) * 1982-08-18 1984-02-24 Matsushita Electric Ind Co Ltd Clock extracting circuit
GB2138227B (en) * 1983-04-12 1987-02-04 Sony Corp Digital video tape recorder apparatus
JPS60206339A (en) * 1984-03-30 1985-10-17 Victor Co Of Japan Ltd Bit clock signal generator of digital signal demodulating device
AU584882B2 (en) * 1984-04-19 1989-06-08 Donson Industries Pty. Ltd. Non-return disc-valve
FR2597689B1 (en) * 1986-04-22 1988-06-10 Trt Telecom Radio Electr DEVICE FOR RECOVERING A RHYTHM SUITABLE IN PARTICULAR FOR AN INFORMATION TRANSMISSION SYSTEM USING IN A TRANSMISSION SENSE THE PRINCIPLE SAID BY A.M.R.T.
US4825448A (en) * 1986-08-07 1989-04-25 International Mobile Machines Corporation Subscriber unit for wireless digital telephone system
JPS63120538A (en) * 1986-11-08 1988-05-24 Nec Corp Timing recovery circuit
AR242878A1 (en) * 1986-11-27 1993-05-31 Siemens Ag Method and circuit for the recovery of the clock and/or the phase of a synchronous or plesiochronous data signal
KR102662413B1 (en) * 2017-12-29 2024-04-30 엘지디스플레이 주식회사 Electrode connection structure for display panel

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2324853C3 (en) * 1973-05-17 1981-09-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Circuit arrangement for recovering the bit clock from a received binary message signal
NL7513610A (en) * 1975-11-21 1977-05-24 Philips Nv RECEIVER FOR SYNCHRONOUS SIGNALS WITH DOUBLE PHASE-LOCKED LOOP.
US4017803A (en) * 1976-01-29 1977-04-12 Sperry Rand Corporation Data recovery system resistant to frequency deviations
DE2621403A1 (en) * 1976-05-14 1977-12-01 Licentia Gmbh Derivation of quasi-synchronous bit cycle from binary signal - using receiver clock pulse generator disconnected when synchronisation word is recognised and reconnecting at following time

Also Published As

Publication number Publication date
EP0006988B1 (en) 1982-05-19
EP0006988A1 (en) 1980-01-23
DK219379A (en) 1979-11-30
DE2962880D1 (en) 1982-07-08
AU526026B2 (en) 1982-12-16
JPS6144422B2 (en) 1986-10-02
BR7903319A (en) 1979-12-11
DE2823343B1 (en) 1979-08-16
JPS54161812A (en) 1979-12-21
ATE1081T1 (en) 1982-06-15

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