DE2621403A1 - Derivation of quasi-synchronous bit cycle from binary signal - using receiver clock pulse generator disconnected when synchronisation word is recognised and reconnecting at following time - Google Patents

Abstract

The circuit derives a quasi-synchronous bit cycle from a binary signal. The signal is divided in equal time intervals (frames) whose beginning is marked by a fixed bit pattern (synchronisation word). A synchronisation word followed by time marking is used at the sender side. When the synchronisation word is recognised at the receiving end a clork pulse generator is switched off. It is switched on again with a fixed specified phase at the following time mark. By using two, alternately switched pulse generator, it is possible to start at exactly defined stipulated time points at high bit pulse frequencies of fixed predetermined phase.

Description

"Procedure and S circuit arrangement for derivation

of an auasi-synchronous bit clock from a binary message signal " The invention relates to a method for deriving a quasi-synchronous bit clock from a binary machine direction signal, which in equal time intervals (frame) is divided and at which the beginning of a time interval by a firmly agreed Bit pattern (Lynchronisationswort) is set and a circuit arrangement for Implementation of the procedure.

To regenerate digital communication signals on longer transmission paths and to be able to process further at the receiving location, it is necessary that this signal underlying bit clock.

Method that exactly determines the bit clock from the message signal by means of a voltage-controlled clock oscillator whose frequency is based on a measurement the phase difference between the input and clock signal is readjusted, gain, are well known under the term "phase-locked loop". Lie are, however relatively complex and not with all data patterns occurring, in particular Can be used for data patterns with few or temporary missing character changes.

In some balls it is sufficient not to exactly set the bit, but rather only with a certain predetermined accuracy with regard to the bit frequency of the To emulate the message signal, which is often done with high-precision, temperature-stabilized Oscillators (quartz oscillators, atomic clocks) is possible. The then remaining one Frequency difference between input and clock signal is through Filling up "empty bits" or by removing "overflow bits" in the process to be processed lMessage signal balanced, but resulting in an error in tmessage transmission has the consequence. Such procedures are known as the "puls-stuffing method" described in the literature (IEEE NEREM-Record 1969, H. 17,. 168-169).

The invention is based on the object in a method of type mentioned to avoid the disadvantages of the prior art. In particular is intended to provide a method and a circuit arrangement for carrying out the method can be specified with which even with any data patterns and low bit frequencies a safe and reliable acquisition of the bit rate is possible in a simple manner is.

The object is achieved according to the invention in that on the transmission side a 'synchronization word is used with the following defined time stamp that on the receiving side when the synchronization word is recognized Clock generator switched off and a clock generator for the subsequent time marking is switched on again with a fixed phase.

With these measures, a quasi-synchronous bit clock can be achieved with any Data patterns, including data patterns in which character changes take a long time lack, derive.

Advantageous refinements and developments of the invention are specified in the subclaims. The method can be used both with a clock generator as well as with two T.ktgenerators. In doing so, the frequency constancy and} 'frequency accuracy of the generators are not very demanding.

Claims 4 and 5 give advantageous circuit arrangements Implementation of the method and have the advantage that they can be easily integrated are. When using two clock generators, which are switched on and off alternately are, there is the advantage that at high bit clock frequencies with a fixed predetermined Phase and thus can be started at precisely defined, predefinable times can.

The frequency constancy as well as the accuracy of the once set Clock frequency of a clock generator only has to be so large be that of too Start of a frame clock generator switched on with the correct phase at the end of this frame has drifted at most by half a bit length in its phase, which means that with a frame length of N = 10n bits the inaccuracy of the clock frequency of the Generator may be around 10-n. The invention will now be based on a Embodiment and Figures 1 and 2 are explained in more detail. Show it: 1 shows a time diagram of the most important signals and functional sequences in FIG Block diagram of an embodiment according to the invention Fig. 3 circuit diagram a controllable bit clock generator.

In the timing diagram in FIG. 1 is in the line labeled E the incoming message signal / is shown, for example, divided into individual frames. The actual synchronization word required for the start of frame detection RSW (syn word) consists only of the first k-1, shown hatched in FIG. 1 Bits, where the (k-1) -th bit is a logic "O" and the other k-2 bits are free are selectable. These k-1 bits are a k-th bit in the form of a logical l'1 "is appended in order to be unambiguous due to the resulting positive signal edge to have a defined time stamp for switching on the respective clock generator.

The rest of the frame is padded with message bits that are in their Entire with "Text" are designated.

As FIG. 2 shows, the input signal S is continuously at the input of a Receive register 10, which by the here for explanation as already available concerned bit clock T is clocked. At the same time, the input signal becomes E by differentiating in a differentiating element 13, a signal Ed is derived which only shows the time stamps at which positive edges occur in the input signal E.

Are the first k-1 bits of the syn word in the receiving register 10 arrived, a yn-word recognition unit 11, for example in the form of a specially, according to the selected syn word wired AND circuit, a detection signal R from, which is differentiated in the differentiating element 12 and thus forms the signal Rd.

Each pulse in the signal Ed sets a first flip-flop 14 in the logic "1" state, while the pulses of the £ signals Rd of this flip-flop reset to the logical "O" state. This is how the signal is created at its output A.

A second flip-flop 15 is triggered by the signal Rd such that it changes its state output signal with an incoming pulse, whereby an output signal B and a negated / B arise. From the two signals A and On the one hand, the signal that controls a first clock generator 31 arises 't1 in that A and B are linked by / member 2: 1, while of the control signal ct2 for a second clock generator 32 by combining A with B in a UiD element 2: 2 arises.

These two control signals St1 and St2, which in their time course exactly the same, but offset from one another by exactly one full frame duration, release the two clock generators alternately, whereby the signals? or Dz can be generated at the outputs. In Fig. 1, these signals T1 and T2 are at one Clock frequency shown, which is slightly lower than the bit clock frequency of the input signal E is, so that in each case the N-th clock pulse is a small value outside the The middle of the bit grid of the first Singangssignal has shifted when the m7aktsignal was exactly in the middle of this grid.

The two signals T1 and T2 are combined in an OR gate 5 on and thus form the desired quasi-synchronous clock g (line cj of Fig. 1).

There is another embodiment of the method according to the invention in that only one clock generator is used, which is used when the respective recognition of the byn word (signal Rd) switched off (blocked) and shortly thereafter by the following Time marking (signal Ed) switched on again with the correct phase in relation to the bit grid (released).

In this simple version of the method, the 2 ktgenerator locked within a bit or a fraction of it and immediately afterwards again are started with the fixed phase position related to the signal Ed, which is easily possible at low bit clock frequencies in this exemplary embodiment With only one clock generator, the second flip-flop 15, the AND gate 22, the clock generator 32, the differentiator 42 and the OR gate 5. The output of the first flip-blops 14 is connected directly to the control input of the clock generator 31 connected so that the control signal A blocks or enables the clock generator.

The output of the differentiator 41 is the clock T directly to the Clock output of the circuit arrangement and to the control input of the receive register 10 from.

It should be noted that in both exemplary embodiments all differentiators only with positive signal edges (transitions from the "O'l level to the 1 "level) emit a signal (Fig. 1).

That recovered and regenerated with the quasi-synchronous bit clock Message signal El (Fig. 1, last line) can, for example, from the first stage of the receiving register 10 can be removed for further processing.

As controllable clock generators can advantageously bare astable Way control / multivibrators are used that are inexpensive and themselves without difficulty, except for a frequency-determining capacitor permit. such a controllable clock generator is shown as an embodiment in Fig. 3 shown. The symbols used there correspond to DIN 40 700 sheet 14, so that there is no need for a detailed explanation of this simple circuit. However, it should be noted that the clock generator is enabled by a logical 1 " and by a logical ': 0' of the control signal via the '-CLEAR inputs of the monostable Nultivibrators is reset to its idle state.

Claims (6)

Claims 8 method for deriving a quasi-synchronous Bit clock from a binary message signal, which is in equal time intervals (Frame) is divided and at which the beginning of a time interval by a fixed agreed bit pattern ('synchronization word) is defined, characterized in that that on the transmit side a synchronization word with the following defined time marking that is used on the receiving side when the synchronization word is recognized a clock generator is switched off and a clock generator for the subsequent time marking is switched on again with a fixed phase. Method according to claim 1, characterized in that only one Clock generator is used. ). The method according to claim 1, characterized in that two im mutual change is switched on for almost the duration of a frame length operated clock generators are used, the clock signals are assembled. 4 '. Circuit arrangement for carrying out the Nupruch method 1 or 2, characterized in that the input signal of a @ynehronization word recognition unit (10, 1) and a first differentiator (eleven) is fed that the output the synchronization word recognition unit (10, 11) with a second differentiator (12) is connected that the first differentiator (13) with mains input (12) input that second differentiator connected to the reset input of a first flip-flop (14) is that at least one clock generator (n1, 32) is provided, which is generated by the output signal of the first flip-flop (14) can be switched on and off and of which the quasi-synchronous Bittakt is removed. 5. Circuit arrangement according to claim 4, characterized in that two clock generators () 1, 2) are provided and the output signal of the first tlip-flop (z4) each a first input of an AND element (r1) and an AND element (22) is fed, the second inputs with the two outputs of a second flip-flop (15) are connected, the control input of which is connected to the output of the second differentiating element (12) is connected that the output of each AND: circuit with an input of a Uaktgenerators (31, 2) is connected, via which the clock generator can be switched on and off is and that the output signals the clock generators to a common, the quasi-synchronous bit clock representing signal are combined. 6. Circuit arrangement according to claim 4, characterized in that the act generator is a controllable astable level vibrator.