EP0004341A1 - Synchronisation d'un oscillateur local avec un oscillateur de référence - Google Patents

Synchronisation d'un oscillateur local avec un oscillateur de référence Download PDF

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Publication number
EP0004341A1
EP0004341A1 EP79100779A EP79100779A EP0004341A1 EP 0004341 A1 EP0004341 A1 EP 0004341A1 EP 79100779 A EP79100779 A EP 79100779A EP 79100779 A EP79100779 A EP 79100779A EP 0004341 A1 EP0004341 A1 EP 0004341A1
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EP
European Patent Office
Prior art keywords
input
output
flip
flop
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP79100779A
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German (de)
English (en)
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EP0004341B1 (fr
Inventor
Jörg Dr. Dr.-Ing. Robra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tekade Felten and Guilleaume Fernmeldeanlagen GmbH
Felten and Guilleaume Fernmeldeanlagen GmbH
Original Assignee
Tekade Felten and Guilleaume Fernmeldeanlagen GmbH
Felten and Guilleaume Fernmeldeanlagen GmbH
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Application filed by Tekade Felten and Guilleaume Fernmeldeanlagen GmbH, Felten and Guilleaume Fernmeldeanlagen GmbH filed Critical Tekade Felten and Guilleaume Fernmeldeanlagen GmbH
Publication of EP0004341A1 publication Critical patent/EP0004341A1/fr
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Publication of EP0004341B1 publication Critical patent/EP0004341B1/fr
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Definitions

  • the invention relates to the synchronization of two oscillations, one of which is derived from a local oscillator and the other from a Reterenz oscillator.
  • the synchronous course of two such vibrations is e.g. required for the proper processing of information transmitted from a sender to a receiver.
  • the local oscillator is an oscillator on the receiver side
  • the reference oscillator means an oscillator on the transmitter side.
  • the transmitted information does not contain any special synchronous signals or is constructed in such a way that synchronization signals can be derived from it.
  • the local oscillator must continue to oscillate at a frequency that is as constant as possible, independent of the reference oscillator, so that after the interruption, the information processing can be continued without further ado.
  • Particularly sensitive to synchronization errors are, for example, transmission systems in which the transmitted information consists of encrypted language. If the synchronization error exceeds a certain limit during the interruption, any further communication is impossible after the interruption because the unveiling process becomes ineffective on the receiver side. In order to keep synchronization errors as small as possible, quartz-controlled oscillators are used.
  • quartz oscillators can only be changed very slightly from the outside - for example via voltage-controlled capacitance diodes, but may have to be changed beyond this limit, for example in the case of very long conversations, in order to achieve synchronization with the reference oscillator, the problem arises, synchronization between to achieve two vibrations, one of which originates from an oscillator, the frequency of which cannot or should not be changed by external interference.
  • Such an oscillator is called a fixed oscillator in the following.
  • the invention has for its object to synchronize the vibrations derived from a fixed oscillator with reference vibrations. This object is achieved by a circuit arrangement with the characterizing features of claim 1.
  • the reference oscillator OL shows in circuit symbols the fixed oscillator OL and a reference oscillator OR, from which the reference oscillations are derived.
  • the example is tailored to the case in which the reference oscillator and the fixed oscillator have nominally the same oscillations rather give frequency.
  • the vibrations of the reference oscillator are conducted via the N-stage frequency divider T1 with the division ratio 2 N : 1.
  • this divider consists of at least one stage.
  • the further stages of the divider T1 can serve the purpose of obtaining a reference oscillation which can be transmitted via a band-limited channel. After the transmission, this vibration is fed to the first input 1 of a phase comparator PC.
  • the second input 2 of this phase comparator is given the frequency of the oscillation of the fixed oscillator OL, which is also divided in the ratio 1: 2.
  • the division is done by the feedback flip-flop FF1 and the divider T2, which consists of N-1 stages.
  • the phase comparator PC checks how corresponding phases of the two input signals - for example the 50% values of the rising edge of the pulses - are shifted in time from one another. In the event of a negative phase time difference, i.e. if the phases of the oscillation derived from the local oscillator lag behind the corresponding phases of the reference oscillation, the phase comparator outputs a binary "1" at its output 1 '. In the opposite case, ie with a positive time difference, a binary "O".
  • FIGS. 2a and 2b show examples of binary signals S at the output of the oscillator OL, at the Q outputs of the two flip-flops FF1 and FF2 and at the output of the gate G3. All signals are plotted on the same time axis. They are provided with the same symbols in the figures as the components at the exit of which they appear. In Fig. 2a the case is treated in which the phase comparator PC on Output 1 'outputs a "0". After what has been said above, the possible changes in state of the flip-flop FF2 then coincide with the rising edges of the oscillator signal.
  • the modulo-2 addition of the output signals of the flip-flops by the gate G3 leads to a signal in which the number of pulses is as large as the difference in the number of pulses of the individual signals.
  • the frequency divider T2 is supplied with a so-called quasi-periodic oscillation, the frequency of which is as large as the difference between half the frequency of the oscillator OL and the frequency of the oscillation which is present at the data input of the flip-flop FF2.
  • the output signal of the gate G3 is now a quasi-periodic oscillation, the frequency of which is as large as the sum of half the frequency of the oscillator OL and the frequency of those oscillations which are present at the data input of the flip-flop FF2.
  • the frequency can be between the two values f / 2 (1 ⁇ 2 -k ).
  • phase comparator PC is a flip-flop of the type already used. It is switched in such a way that its data input coincides with the first input 1, its clock input with the second input 2 and its 3 output with the output 1 'of the phase comparator . If a rising edge on input 2 reaches the phase comparator PC before the corresponding edge of the reference oscillation, ie if there is a positive phase time difference, then the "1" at the data input of the flip-flop is adopted at the 1 output, which means that the Q Output is set to "0". If the phase time difference is negative, the "0" at the data input is sent to the Q Output accepted and thus the Q output set to "1".
  • a controllable changeover switch U which switches the data input when a maximum permissible phase time difference is exceeded of the second flip-flop FF2 connects to the output of a stage of the divider T2 at which a binary oscillation with a higher frequency is present.
  • the switch U is controlled by a second output 2 'of the phase comparator PC. If, for example, a binary "1" occurs at this output, the contact path of the switch is switched to the output of a stage of the divider T2 which is further on the input side.
  • FIG. 3 shows a possible embodiment of the phase comparator for this case.
  • the shift register SR which in the exemplary embodiment consists of three stages, is coupled with its data input to the output of the divider T2.
  • the first stage of the shift register SR is connected to the first negated input of the OR gate G4 and the last stage of the register is connected to the second non-negated input of this gate.
  • the output of the gate G4 has a "0" if and only if a "1" is stored in the first stage of the register and a "0" in the last stage, ie if the shift register SR is being traversed by a rising edge. If the corresponding rising edge of the reference signal occurs at input 1 at this moment, the "0" at the output of gate G4 is transferred to the Q output of flip-flop FF4.
  • the switch Since this output is connected to the control input of the switch U, the switch is not actuated. If the output of the gate G4 leads to a "1" and then a rising edge occurs in the reference signal, the phase time difference is three clock pulses of the clock signal for the shift register SR. The "1" transmitted at the control input of the switch U now leads to its actuation.
  • the flip-flop FF3 whose data input is connected to the middle stage of the shift register SR and at whose clock input the reference signal is present, controls the gate G2 with its Q output. If the connection between the reference oscillator and the local oscillator is interrupted, the vibrations derived from the local oscillator should be used without correction.
  • an evaluator AW is provided which outputs a "1" to the reset input of the flip-flop FF2 if the reference oscillation does not occur. This will make the Q -Output of this flip-flop forced to "1” or the Q output to "0". The oscillation coming from the local oscillator via the flip-flop FF1 is now not changed by the gate G3.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
EP79100779A 1978-03-17 1979-03-15 Synchronisation d'un oscillateur local avec un oscillateur de référence Expired EP0004341B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2811636 1978-03-17
DE19782811636 DE2811636A1 (de) 1978-03-17 1978-03-17 Synchronisation eines lokalen oszillators mit einem referenzoszillator

Publications (2)

Publication Number Publication Date
EP0004341A1 true EP0004341A1 (fr) 1979-10-03
EP0004341B1 EP0004341B1 (fr) 1981-09-23

Family

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Family Applications (1)

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EP79100779A Expired EP0004341B1 (fr) 1978-03-17 1979-03-15 Synchronisation d'un oscillateur local avec un oscillateur de référence

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EP (1) EP0004341B1 (fr)
AT (1) AT377874B (fr)
DE (2) DE2811636A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2466911A1 (fr) * 1979-09-27 1981-04-10 Communications Satellite Corp Boucle d'accrochage de phase digitale pour frequence mit (module d'interface terrestre)
WO1985002731A1 (fr) * 1983-12-14 1985-06-20 Telefunken Fernseh Und Rundfunk Gmbh Circuit de reglage de phase

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0396015A (ja) * 1989-09-08 1991-04-22 Oki Electric Ind Co Ltd 高速デジタルｐｌｌ装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB982327A (en) * 1961-11-08 1965-02-03 Gen Electric Co Ltd Improvements in or relating to apparatus for supplying an electric timing signal under the control of an input electric signal
US3344361A (en) * 1964-10-28 1967-09-26 Aga Ab Phase controlled oscillator loop including an electronic counter
DE1537166A1 (de) * 1966-08-19 1969-09-18 Int Standard Electric Corp Verfahren zur Phasensynchronisierung eines Oszillators
DE2119091A1 (de) * 1970-04-22 1971-11-04 Int Standard Electric Corp Spannungsgesteuerter Taktgenerator
US3694752A (en) * 1971-03-18 1972-09-26 North American Rockwell High speed transmission receiver utilizing fine receiver timing and carrier phase recovery
US3755748A (en) * 1972-03-06 1973-08-28 Motorola Inc Digital phase shifter/synchronizer and method of shifting
US3919647A (en) * 1973-10-29 1975-11-11 Siemens Ag Circuit arrangement for adjusting the phase state of a timing signal

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB982327A (en) * 1961-11-08 1965-02-03 Gen Electric Co Ltd Improvements in or relating to apparatus for supplying an electric timing signal under the control of an input electric signal
US3344361A (en) * 1964-10-28 1967-09-26 Aga Ab Phase controlled oscillator loop including an electronic counter
DE1537166A1 (de) * 1966-08-19 1969-09-18 Int Standard Electric Corp Verfahren zur Phasensynchronisierung eines Oszillators
DE2119091A1 (de) * 1970-04-22 1971-11-04 Int Standard Electric Corp Spannungsgesteuerter Taktgenerator
US3694752A (en) * 1971-03-18 1972-09-26 North American Rockwell High speed transmission receiver utilizing fine receiver timing and carrier phase recovery
US3755748A (en) * 1972-03-06 1973-08-28 Motorola Inc Digital phase shifter/synchronizer and method of shifting
US3919647A (en) * 1973-10-29 1975-11-11 Siemens Ag Circuit arrangement for adjusting the phase state of a timing signal

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRICAL DESIGN NEWS, Vol. 17, Nr. 6, 15. Marz 1972, Denver, US, JOHNSON: "LOW-power digital phase locked loop utilizes CMOS logic", Seiten 36-39 * Seite 36, linke Spalte, Zeile 15 - Seite 37, rechte Spalte, Zeile 22; Figuren 1, 3 * *
ELECTRONIC ENGINEERING, Vol. 45, Nr. 595, August 1977, London, GB, SHUM: "Adaptive bandwidth binary digital phase locked loop", Seiten 26, 27 * Seite 26, linke Spalte; Figur 1 * *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2466911A1 (fr) * 1979-09-27 1981-04-10 Communications Satellite Corp Boucle d'accrochage de phase digitale pour frequence mit (module d'interface terrestre)
WO1985002731A1 (fr) * 1983-12-14 1985-06-20 Telefunken Fernseh Und Rundfunk Gmbh Circuit de reglage de phase
US4639687A (en) * 1983-12-14 1987-01-27 Telefunken Fernseh Und Rundfunk Gmbh Phase control circuit
AU585845B2 (en) * 1983-12-14 1989-06-29 Telefunken Fernseh Und Rundfunk Gmbh Phase regulation circuit

Also Published As

Publication number Publication date
ATA197279A (de) 1984-09-15
DE2960869D1 (en) 1981-12-10
DE2811636A1 (de) 1979-09-20
EP0004341B1 (fr) 1981-09-23
AT377874B (de) 1985-05-10

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