EP0000326B1 - Verfahren zum Herstellen sehr kleiner, mit Störstellen versehener Zonen in einem Halbleitersubstrat - Google Patents

Verfahren zum Herstellen sehr kleiner, mit Störstellen versehener Zonen in einem Halbleitersubstrat Download PDF

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Publication number
EP0000326B1
EP0000326B1 EP78100081A EP78100081A EP0000326B1 EP 0000326 B1 EP0000326 B1 EP 0000326B1 EP 78100081 A EP78100081 A EP 78100081A EP 78100081 A EP78100081 A EP 78100081A EP 0000326 B1 EP0000326 B1 EP 0000326B1
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Prior art keywords
layer
window
etching
silicon dioxide
silicon nitride
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German (de)
English (en)
French (fr)
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EP0000326A1 (de
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Bai-Cwo Feng
George Cheng-Cwo Feng
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Definitions

  • the invention relates to a method for producing a zone doped with an interference element within a desired region of the surface of a semiconductor substrate by forming a first mask layer consisting of a lower and an upper layer, the materials of which can be selectively etched, and by etching a first defining the aforementioned region Opening in the first mask layer such that part of the upper layer overhangs the lower layer.
  • Alignment methods commonly used today use alignment marks on the mask and in the underlying semiconductor substrate. These brands are hand-aligned by experienced operators. As the size of the individual components and semiconductor circuits decreases, the possibility of alignment errors increases. This method is also considerably more expensive than an alignment which arises automatically in a production method, since each mask must be aligned individually.
  • U.S. Patents 3,928,082, 3,948,694, 3,967,981 and Applicant's U.S. Patent 3,900,352 are examples of such a self-aligning orientation.
  • the use of these methods in production is limited either by the required ion implantation of one or more interfering elements in areas through a mask or because they are only suitable for the production of distant zones.
  • FR-A 2 130 397 which corresponds to DE-OS 22 12 049, discloses a method for aligning a zone doped with interfering elements within another such zone with the aid of a mask layer consisting of two partial layers which can be selectively etched with respect to one another, whereby here the alignment of the two zones with one another is achieved by an undercut achieved by undercutting.
  • a difficulty that has not been correctly recognized in the design and manufacture of semiconductor circuits by known methods is the lateral undercutting of a mask layer which lies under another mask layer during an etching process. This under-etching increases the effective size of the opening in the mask for the intrusion of interfering elements and can result in an overlap of zones which should be separate in themselves.
  • the object of the invention is therefore to provide an improved method for the self-aligning penetration of an interference element into a) a semiconductor substrate or in b) another region within the substrate doped with interference elements.
  • this should make it possible to produce two or more zones doped with interference elements within a substrate or another zone doped with interference elements, these two or more zones being automatically aligned with one another.
  • this object of the invention is achieved in that the undercut or undercut resulting from the etching of a composite mask of, for example, silicon nitride and silicon dioxide is advantageously used.
  • this undercut or undercut is used to ensure that between the perimeter of a zone doped with interfering elements and another, i.e. For example, the emitter and base zones of a planar transistor are kept at a predetermined minimum distance.
  • the starting position for the invention consists first of all in that a first mask layer is produced on the surface of a substrate, said mask layer consisting of a lower and an upper material which can be selectively etched with respect to one another, that a first opening in the first mask layer is subsequently provided within the first mask layer It is etched in such a way that part of the upper layer at the periphery of the first opening forms an overhang over the lower layer.
  • a second mask layer is then formed within the first opening, including a layer of material that can be etched with the same etchant is like the upper layer, so that the overhang is at least partially filled and the entire material that can be etched with the same etching material is thinner inside the opening than on its circumference.
  • a second opening is then etched within the first opening by means of a barrier mask through the second mask layer, whereupon an interference element is introduced through this second opening to form a doped zone.
  • the undercut is etched down to about 0.7 microns.
  • a base zone is formed within the first opening.
  • An emitter zone is then formed within the second opening. If everything is carried out in this way, a distance between the circumference of the emitter zone and the circumference of the base zone of approximately 0.7 micrometers is obtained, so that an automatic alignment is ensured in this way.
  • An advantageous further feature of the invention is that more than one zone can be formed within the base zone.
  • emitter and base contacts can only be made by using a blocking mask with automatic alignment.
  • FIG. 1A shows a partially completed bipolar transistor, which has been manufactured by previously customary methods.
  • An N + -type buried layer 7 lies partly in a P-type semiconductor substrate 2 and partly within an N-type epitaxial layer 6.
  • This subcollector zone is normally produced by first diffusing arsenic into the substrate 2 as an interfering element and then an N - compassionc! 2.
  • Epitaxial layer 6 can grow thereon up to a thickness of about 2.0 micrometers.
  • the substrate also contains a P + - conductive insulation diffusion 4 which surrounds the sub-collector zone 7.
  • the P + - conductive insulation diffusion 4 is usually produced by diffusing boron as a disturbing element into the semiconductor body 2 before the epitaxial precipitation, so that in the subsequent production of the epitaxial layer the P + - conductive insulation diffusion penetrates into the epitaxial layer 6 by diffusion.
  • the methods for producing the sub-collector zone and the insulation diffusion zone are generally known to the person skilled in the art and can be carried out in various ways.
  • the thickness of the epitaxial layer 6 can be less than or greater than 2.0 micrometers.
  • three mask layers 8, 10 and 12 are applied, which preferably consist of silicon dioxide, silicon nitride or silicon dioxide in this order.
  • the mask layer 8 is thermally grown on the epitaxial layer 6 to a thickness of approximately 140 to 200 nm.
  • the silicon nitride layer 10 can be deposited by chemical precipitation from the vapor phase to a thickness between 50 and 150 nm. Instead, the mask layer 10 can also consist of silicon oxynitride.
  • the mask layer 12 consists of silicon dioxide chemically deposited from the vapor phase. This silicon dioxide layer 12 only has the task of masking the nitride layer 10, since etching agents, such as hot phosphoric acid, which attack the silicon nitride, also attack normal photoresists.
  • the layer 12 applied by chemical precipitation from the vapor phase can be replaced by a silicon oxide layer applied by cathode sputtering or other known masks.
  • the mask layer 12 can also be omitted entirely if the etching is carried out as plasma etching. This type of etching is commonly referred to as reactive ion or plasma etching.
  • the nitride layer 10 can be etched using a mixture of gaseous CF 4 and O 2 in a plasma system using the AZ1350H photoresist as a mask.
  • openings are etched into the silicon dioxide layer 12 using a mask that delimits the various zones in the transistor.
  • the base zone, the connection zone for the sub-collector zone and the isolation zones are defined by the mask.
  • Other zones for example Schottky junction diodes and resistors, can be defined by the same mask at adjacent locations in the epitaxial layer 6.
  • the Schottky junction diode and resistor that can be fabricated with the transistor are not shown. However, their manufacture follows the same process steps as the formation of the connection zone 11 for the sub-collector, which will be described.
  • the mask defining the dimensions, which delimits the different zones, generally consists of a photoresist, such as AZ1350J from Shipley, which is exposed and developed in the usual way.
  • the pyrolytically deposited silicon dioxide layer 12 can be etched by means of a solution of a hydrofluoric acid buffered in ammonium fluoride, this etchant silicon nitride in the essentially does not attack.
  • the areas of the nitride layer 10 exposed in the openings of the silicon dioxide layer 12 are then etched off in hot phosphoric acid or in any other etchant which does not attack the silicon dioxide. During this etching step, the areas separating the sub-collector and the isolation zone are masked by the photoresist. Certain zones are thus defined in the silicon dioxide layer 12 in this method step.
  • a blocking mask consisting of photoresist is used to produce an opening for the sub-collector connection and an opening for the resistance region (not shown).
  • the location of the sub-collector zone and the resistance areas is further defined by etching the exposed areas of the silicon nitride layer 10 in hot phosphoric acid or any other etchant that does not attack silicon dioxide. After these openings are made in the silicon nitride layer 10, the semiconductor die is exposed to an etchant which attacks the regions of the oxide layer 8 which are exposed in the openings of the silicon nitride layer 10. Hydrofluoric acid buffered in ammonium fluoride is preferably used to etch the silicon dioxide layer 8.
  • the dopant for the sub-collector is usually phosphorus, although arsenic or another Group V interfering element can also be used.
  • the phosphorus is driven in at a temperature of 1000 ° C. in an oxidizing atmosphere, as a result of which an oxide layer grows to a thickness of approximately 140 nm, as shown in FIG. 1D.
  • the pyrolytically deposited oxide layer 12 has been stripped off and the N + -type connection region 11 for the sub-collector zone and the additional resistance region (not shown) have been completed.
  • the substrate is completely covered with a thermally grown silicon dioxide layer 8 and the remaining zones still to be produced are defined by the silicon nitride layer 10.
  • an opening is made through the silicon dioxide layer 8 after the P + - conducting zone 17.
  • the thermally grown silicon dioxide layer over the N-conductive zone 14, the continuous connection zone 11 and the resistance area are protected by the barrier mask 18.
  • a diffusion of P-conductive material, such as boron, is then carried out in the exposed area, as a result of which the P + -conductive insulation zone 17 according to FIG. 1E is formed.
  • another barrier mask 22 is used to protect all areas of the substrate with the exception of zone 14. Then an opening is made in the silicon dioxide layer 8 to expose the zone 14.
  • This etching process results in an undercut of the silicon nitride layer 10 in the regions 15, i. H. that a narrow band of silicon dioxide is removed from under the silicon nitride layer so that an overhang arises.
  • This undercut is critical to the present invention and must be closely monitored when the silicon dioxide layer 8 is etched in buffered hydrofluoric acid.
  • the etching rate of thermally grown silicon dioxide in 7: 1 buffered hydrofluoric acid at 31 ° C is about 160 nm per minute.
  • the etching is continued until an undercut of about 0.6 to 0.7 micrometers is achieved.
  • the etching could also be carried out by means of a plasma etching for a precisely monitored undercut.
  • the P-type base zone 24 is diffused into the N-type epitaxial zone 6.
  • the base zone can also be fabricated by ion implantation and subsequent driving, giving essentially the same type of base zone.
  • the diffusion opening defined by the thermally grown silicon dioxide layer 8 is wider on each side by at least 0.6 to 0.7 microns than the opening formed in the silicon nitride layer 10.
  • BBr 3 is deposited in a dry oxygen and argon atmosphere at about 875 ° C as borosilicate glass to a thickness of about 40 nm.
  • the glass is etched in buffered hydrofluoric acid to remove the entire glass layer and the base is formed by conventional driving in and a reoxidation process which takes place at 925 ° C. in water vapor and oxygen.
  • This forms a layer 26 of thermally grown silicon oxide with a thickness of 80 nm above the base zone and the insulation regions, as shown in FIG. 1G.
  • the oxide layer 26 also forms under the overhang made of silicon nitride.
  • P-type zones 17 and 24 can be formed simultaneously, which of course depends on the process parameters.
  • layers of silicon nitride and silicon dioxide which are denoted by 28 and 30 respectively, are sequentially removed by chemical ashamedy from the vapor phase or applied by sputtering.
  • the thickness of layers 28 and 30 is preferably approximately 100 nm.
  • Layer 30 serves only as a mask during a wet etching process with hot phosphoric acid. for the silicon nitride layer 28. This overlap completely fills up the overhang below the silicon nitride layer at the undercut zone 15.
  • the composition and thickness of the materials deposited here can be different. For example, what is less desirable, the base oxide layer 26 could be made thicker so that the undercut zone 15 is completely filled without the need for silicon nitride.
  • silicon nitride could be replaced by silicon oxynitride or another mask material.
  • layer 28 could be silicon oxynitride and layer 10 silicon nitride, or vice versa.
  • the important consideration here is that the thickness of the mask layer at the periphery of the base opening is greater than the thickness of the mask layer inside the opening, both of which can be etched with the same etchant. In this way, blocking masks can be used to define the emitter zone and other zones doped with interfering elements without the difficulty of etching down to the protected areas of the substrate.
  • a single mask 29 is then fabricated to form openings on the oxide layer 30 to form the base contact and the emitter zones above the base zone 24. The embodiment shown here shows a single opening intended for base contact.
  • two or more contacts can also be formed on each side of the emitter.
  • the width of the emitter within the base zone 24 is carefully controlled by the new method. This is made possible by the completely filled undercut 15 and the double mask layers on the circumference of the base opening. Since this defines the emitter opening exactly, this double mask layer prevents the emitter from diffusing too close towards the circumference of the base zone 24 to the side.
  • the silicon dioxide layer 30 is then etched through the barrier mask 29 to produce the openings 31, 32 and 33.
  • the silicon nitride is etched away at the exposed areas, using the silicon dioxide layer 30 as a mask.
  • a second barrier mask 35 which protects the zone 31 against etching, is then used to etch the thermally grown silicon dioxide layer 26 in the openings 32 and 33 shown in FIG. 1.
  • a conventional etching method using buffered hydrofluoric acid or plasma etching is used to expose the openings 32 'and 33' to the surface of the layer 6.
  • the emitter zone is then formed in the usual way, for example by the diffusion of arsenic. In the same way, the conductivity in the connection area 11 is increased by arsenic diffusion in the area 40.
  • An opening for a Schottky junction diode can be made during this process step down to the epitaxial layer 6 in an area that is not shown here.
  • Contact with the base zone can be made by closing openings 32 and 33 with a barrier mask while leaving the portion of silicon dioxide layer 26 exposed within opening 31 free. It may be desirable to deposit a thin shielding oxide layer with a thickness of approximately 10 nm in the area of the emitter and subcollector zones, in order to thereby protect these zones against contamination by the photoresist. The oxide in opening 31 is then removed, exposing the base contact area for subsequent metallization (not shown).
  • FIG. 2 shows a top view of the transistor in the process state shown in FIG. 1, wherein the automatic alignment of the emitter zone 36 within the base zone 24 can be seen. Because of the undercut previously discussed, there will always be a selected distance between the edge of the emitter zone 36 and the edge of the base zone 34. In the current state of the art, this undercut is at least 0.7 microns wide.
  • the mask for the base zone defined by the silicon nitride layer 10 and the opening for the base diffusion defined by the oxide layer 8 in FIG. 1F are designated by the reference numerals 43 and 44.
  • the mask for the emitter zone is defined by the opening 32 'and the opening defined by the blocking mask 35 is identified by 35'. Both of these masks are intentionally not correctly aligned with each other, but this has no effect on the alignment of the emitter zone in the novel method according to the invention. It should also be noted that the emitter mask 32 'overlaps the base mask 43, which shows what tolerances are possible in the mask design with the new method.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
EP78100081A 1977-07-12 1978-06-02 Verfahren zum Herstellen sehr kleiner, mit Störstellen versehener Zonen in einem Halbleitersubstrat Expired EP0000326B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/814,829 US4131497A (en) 1977-07-12 1977-07-12 Method of manufacturing self-aligned semiconductor devices
US814829 1991-12-31

Publications (2)

Publication Number Publication Date
EP0000326A1 EP0000326A1 (de) 1979-01-24
EP0000326B1 true EP0000326B1 (de) 1980-09-17

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US (1) US4131497A (enrdf_load_stackoverflow)
EP (1) EP0000326B1 (enrdf_load_stackoverflow)
JP (1) JPS5419677A (enrdf_load_stackoverflow)
DE (1) DE2860161D1 (enrdf_load_stackoverflow)

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US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
CN104756230B (zh) * 2012-10-26 2018-11-02 应用材料公司 组合掩模

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Also Published As

Publication number Publication date
EP0000326A1 (de) 1979-01-24
DE2860161D1 (en) 1980-12-18
US4131497A (en) 1978-12-26
JPS6138623B2 (enrdf_load_stackoverflow) 1986-08-30
JPS5419677A (en) 1979-02-14

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