EP0000326B1 - Method of forming very small impurity regions in a semiconductor substrate - Google Patents

Method of forming very small impurity regions in a semiconductor substrate Download PDF

Info

Publication number
EP0000326B1
EP0000326B1 EP78100081A EP78100081A EP0000326B1 EP 0000326 B1 EP0000326 B1 EP 0000326B1 EP 78100081 A EP78100081 A EP 78100081A EP 78100081 A EP78100081 A EP 78100081A EP 0000326 B1 EP0000326 B1 EP 0000326B1
Authority
EP
European Patent Office
Prior art keywords
layer
window
etching
silicon dioxide
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78100081A
Other languages
German (de)
French (fr)
Other versions
EP0000326A1 (en
Inventor
Bai-Cwo Feng
George Cheng-Cwo Feng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0000326A1 publication Critical patent/EP0000326A1/en
Application granted granted Critical
Publication of EP0000326B1 publication Critical patent/EP0000326B1/en
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Definitions

  • the invention relates to a method for producing a zone doped with an interference element within a desired region of the surface of a semiconductor substrate by forming a first mask layer consisting of a lower and an upper layer, the materials of which can be selectively etched, and by etching a first defining the aforementioned region Opening in the first mask layer such that part of the upper layer overhangs the lower layer.
  • Alignment methods commonly used today use alignment marks on the mask and in the underlying semiconductor substrate. These brands are hand-aligned by experienced operators. As the size of the individual components and semiconductor circuits decreases, the possibility of alignment errors increases. This method is also considerably more expensive than an alignment which arises automatically in a production method, since each mask must be aligned individually.
  • U.S. Patents 3,928,082, 3,948,694, 3,967,981 and Applicant's U.S. Patent 3,900,352 are examples of such a self-aligning orientation.
  • the use of these methods in production is limited either by the required ion implantation of one or more interfering elements in areas through a mask or because they are only suitable for the production of distant zones.
  • FR-A 2 130 397 which corresponds to DE-OS 22 12 049, discloses a method for aligning a zone doped with interfering elements within another such zone with the aid of a mask layer consisting of two partial layers which can be selectively etched with respect to one another, whereby here the alignment of the two zones with one another is achieved by an undercut achieved by undercutting.
  • a difficulty that has not been correctly recognized in the design and manufacture of semiconductor circuits by known methods is the lateral undercutting of a mask layer which lies under another mask layer during an etching process. This under-etching increases the effective size of the opening in the mask for the intrusion of interfering elements and can result in an overlap of zones which should be separate in themselves.
  • the object of the invention is therefore to provide an improved method for the self-aligning penetration of an interference element into a) a semiconductor substrate or in b) another region within the substrate doped with interference elements.
  • this should make it possible to produce two or more zones doped with interference elements within a substrate or another zone doped with interference elements, these two or more zones being automatically aligned with one another.
  • this object of the invention is achieved in that the undercut or undercut resulting from the etching of a composite mask of, for example, silicon nitride and silicon dioxide is advantageously used.
  • this undercut or undercut is used to ensure that between the perimeter of a zone doped with interfering elements and another, i.e. For example, the emitter and base zones of a planar transistor are kept at a predetermined minimum distance.
  • the starting position for the invention consists first of all in that a first mask layer is produced on the surface of a substrate, said mask layer consisting of a lower and an upper material which can be selectively etched with respect to one another, that a first opening in the first mask layer is subsequently provided within the first mask layer It is etched in such a way that part of the upper layer at the periphery of the first opening forms an overhang over the lower layer.
  • a second mask layer is then formed within the first opening, including a layer of material that can be etched with the same etchant is like the upper layer, so that the overhang is at least partially filled and the entire material that can be etched with the same etching material is thinner inside the opening than on its circumference.
  • a second opening is then etched within the first opening by means of a barrier mask through the second mask layer, whereupon an interference element is introduced through this second opening to form a doped zone.
  • the undercut is etched down to about 0.7 microns.
  • a base zone is formed within the first opening.
  • An emitter zone is then formed within the second opening. If everything is carried out in this way, a distance between the circumference of the emitter zone and the circumference of the base zone of approximately 0.7 micrometers is obtained, so that an automatic alignment is ensured in this way.
  • An advantageous further feature of the invention is that more than one zone can be formed within the base zone.
  • emitter and base contacts can only be made by using a blocking mask with automatic alignment.
  • FIG. 1A shows a partially completed bipolar transistor, which has been manufactured by previously customary methods.
  • An N + -type buried layer 7 lies partly in a P-type semiconductor substrate 2 and partly within an N-type epitaxial layer 6.
  • This subcollector zone is normally produced by first diffusing arsenic into the substrate 2 as an interfering element and then an N - compassionc! 2.
  • Epitaxial layer 6 can grow thereon up to a thickness of about 2.0 micrometers.
  • the substrate also contains a P + - conductive insulation diffusion 4 which surrounds the sub-collector zone 7.
  • the P + - conductive insulation diffusion 4 is usually produced by diffusing boron as a disturbing element into the semiconductor body 2 before the epitaxial precipitation, so that in the subsequent production of the epitaxial layer the P + - conductive insulation diffusion penetrates into the epitaxial layer 6 by diffusion.
  • the methods for producing the sub-collector zone and the insulation diffusion zone are generally known to the person skilled in the art and can be carried out in various ways.
  • the thickness of the epitaxial layer 6 can be less than or greater than 2.0 micrometers.
  • three mask layers 8, 10 and 12 are applied, which preferably consist of silicon dioxide, silicon nitride or silicon dioxide in this order.
  • the mask layer 8 is thermally grown on the epitaxial layer 6 to a thickness of approximately 140 to 200 nm.
  • the silicon nitride layer 10 can be deposited by chemical precipitation from the vapor phase to a thickness between 50 and 150 nm. Instead, the mask layer 10 can also consist of silicon oxynitride.
  • the mask layer 12 consists of silicon dioxide chemically deposited from the vapor phase. This silicon dioxide layer 12 only has the task of masking the nitride layer 10, since etching agents, such as hot phosphoric acid, which attack the silicon nitride, also attack normal photoresists.
  • the layer 12 applied by chemical precipitation from the vapor phase can be replaced by a silicon oxide layer applied by cathode sputtering or other known masks.
  • the mask layer 12 can also be omitted entirely if the etching is carried out as plasma etching. This type of etching is commonly referred to as reactive ion or plasma etching.
  • the nitride layer 10 can be etched using a mixture of gaseous CF 4 and O 2 in a plasma system using the AZ1350H photoresist as a mask.
  • openings are etched into the silicon dioxide layer 12 using a mask that delimits the various zones in the transistor.
  • the base zone, the connection zone for the sub-collector zone and the isolation zones are defined by the mask.
  • Other zones for example Schottky junction diodes and resistors, can be defined by the same mask at adjacent locations in the epitaxial layer 6.
  • the Schottky junction diode and resistor that can be fabricated with the transistor are not shown. However, their manufacture follows the same process steps as the formation of the connection zone 11 for the sub-collector, which will be described.
  • the mask defining the dimensions, which delimits the different zones, generally consists of a photoresist, such as AZ1350J from Shipley, which is exposed and developed in the usual way.
  • the pyrolytically deposited silicon dioxide layer 12 can be etched by means of a solution of a hydrofluoric acid buffered in ammonium fluoride, this etchant silicon nitride in the essentially does not attack.
  • the areas of the nitride layer 10 exposed in the openings of the silicon dioxide layer 12 are then etched off in hot phosphoric acid or in any other etchant which does not attack the silicon dioxide. During this etching step, the areas separating the sub-collector and the isolation zone are masked by the photoresist. Certain zones are thus defined in the silicon dioxide layer 12 in this method step.
  • a blocking mask consisting of photoresist is used to produce an opening for the sub-collector connection and an opening for the resistance region (not shown).
  • the location of the sub-collector zone and the resistance areas is further defined by etching the exposed areas of the silicon nitride layer 10 in hot phosphoric acid or any other etchant that does not attack silicon dioxide. After these openings are made in the silicon nitride layer 10, the semiconductor die is exposed to an etchant which attacks the regions of the oxide layer 8 which are exposed in the openings of the silicon nitride layer 10. Hydrofluoric acid buffered in ammonium fluoride is preferably used to etch the silicon dioxide layer 8.
  • the dopant for the sub-collector is usually phosphorus, although arsenic or another Group V interfering element can also be used.
  • the phosphorus is driven in at a temperature of 1000 ° C. in an oxidizing atmosphere, as a result of which an oxide layer grows to a thickness of approximately 140 nm, as shown in FIG. 1D.
  • the pyrolytically deposited oxide layer 12 has been stripped off and the N + -type connection region 11 for the sub-collector zone and the additional resistance region (not shown) have been completed.
  • the substrate is completely covered with a thermally grown silicon dioxide layer 8 and the remaining zones still to be produced are defined by the silicon nitride layer 10.
  • an opening is made through the silicon dioxide layer 8 after the P + - conducting zone 17.
  • the thermally grown silicon dioxide layer over the N-conductive zone 14, the continuous connection zone 11 and the resistance area are protected by the barrier mask 18.
  • a diffusion of P-conductive material, such as boron, is then carried out in the exposed area, as a result of which the P + -conductive insulation zone 17 according to FIG. 1E is formed.
  • another barrier mask 22 is used to protect all areas of the substrate with the exception of zone 14. Then an opening is made in the silicon dioxide layer 8 to expose the zone 14.
  • This etching process results in an undercut of the silicon nitride layer 10 in the regions 15, i. H. that a narrow band of silicon dioxide is removed from under the silicon nitride layer so that an overhang arises.
  • This undercut is critical to the present invention and must be closely monitored when the silicon dioxide layer 8 is etched in buffered hydrofluoric acid.
  • the etching rate of thermally grown silicon dioxide in 7: 1 buffered hydrofluoric acid at 31 ° C is about 160 nm per minute.
  • the etching is continued until an undercut of about 0.6 to 0.7 micrometers is achieved.
  • the etching could also be carried out by means of a plasma etching for a precisely monitored undercut.
  • the P-type base zone 24 is diffused into the N-type epitaxial zone 6.
  • the base zone can also be fabricated by ion implantation and subsequent driving, giving essentially the same type of base zone.
  • the diffusion opening defined by the thermally grown silicon dioxide layer 8 is wider on each side by at least 0.6 to 0.7 microns than the opening formed in the silicon nitride layer 10.
  • BBr 3 is deposited in a dry oxygen and argon atmosphere at about 875 ° C as borosilicate glass to a thickness of about 40 nm.
  • the glass is etched in buffered hydrofluoric acid to remove the entire glass layer and the base is formed by conventional driving in and a reoxidation process which takes place at 925 ° C. in water vapor and oxygen.
  • This forms a layer 26 of thermally grown silicon oxide with a thickness of 80 nm above the base zone and the insulation regions, as shown in FIG. 1G.
  • the oxide layer 26 also forms under the overhang made of silicon nitride.
  • P-type zones 17 and 24 can be formed simultaneously, which of course depends on the process parameters.
  • layers of silicon nitride and silicon dioxide which are denoted by 28 and 30 respectively, are sequentially removed by chemical ashamedy from the vapor phase or applied by sputtering.
  • the thickness of layers 28 and 30 is preferably approximately 100 nm.
  • Layer 30 serves only as a mask during a wet etching process with hot phosphoric acid. for the silicon nitride layer 28. This overlap completely fills up the overhang below the silicon nitride layer at the undercut zone 15.
  • the composition and thickness of the materials deposited here can be different. For example, what is less desirable, the base oxide layer 26 could be made thicker so that the undercut zone 15 is completely filled without the need for silicon nitride.
  • silicon nitride could be replaced by silicon oxynitride or another mask material.
  • layer 28 could be silicon oxynitride and layer 10 silicon nitride, or vice versa.
  • the important consideration here is that the thickness of the mask layer at the periphery of the base opening is greater than the thickness of the mask layer inside the opening, both of which can be etched with the same etchant. In this way, blocking masks can be used to define the emitter zone and other zones doped with interfering elements without the difficulty of etching down to the protected areas of the substrate.
  • a single mask 29 is then fabricated to form openings on the oxide layer 30 to form the base contact and the emitter zones above the base zone 24. The embodiment shown here shows a single opening intended for base contact.
  • two or more contacts can also be formed on each side of the emitter.
  • the width of the emitter within the base zone 24 is carefully controlled by the new method. This is made possible by the completely filled undercut 15 and the double mask layers on the circumference of the base opening. Since this defines the emitter opening exactly, this double mask layer prevents the emitter from diffusing too close towards the circumference of the base zone 24 to the side.
  • the silicon dioxide layer 30 is then etched through the barrier mask 29 to produce the openings 31, 32 and 33.
  • the silicon nitride is etched away at the exposed areas, using the silicon dioxide layer 30 as a mask.
  • a second barrier mask 35 which protects the zone 31 against etching, is then used to etch the thermally grown silicon dioxide layer 26 in the openings 32 and 33 shown in FIG. 1.
  • a conventional etching method using buffered hydrofluoric acid or plasma etching is used to expose the openings 32 'and 33' to the surface of the layer 6.
  • the emitter zone is then formed in the usual way, for example by the diffusion of arsenic. In the same way, the conductivity in the connection area 11 is increased by arsenic diffusion in the area 40.
  • An opening for a Schottky junction diode can be made during this process step down to the epitaxial layer 6 in an area that is not shown here.
  • Contact with the base zone can be made by closing openings 32 and 33 with a barrier mask while leaving the portion of silicon dioxide layer 26 exposed within opening 31 free. It may be desirable to deposit a thin shielding oxide layer with a thickness of approximately 10 nm in the area of the emitter and subcollector zones, in order to thereby protect these zones against contamination by the photoresist. The oxide in opening 31 is then removed, exposing the base contact area for subsequent metallization (not shown).
  • FIG. 2 shows a top view of the transistor in the process state shown in FIG. 1, wherein the automatic alignment of the emitter zone 36 within the base zone 24 can be seen. Because of the undercut previously discussed, there will always be a selected distance between the edge of the emitter zone 36 and the edge of the base zone 34. In the current state of the art, this undercut is at least 0.7 microns wide.
  • the mask for the base zone defined by the silicon nitride layer 10 and the opening for the base diffusion defined by the oxide layer 8 in FIG. 1F are designated by the reference numerals 43 and 44.
  • the mask for the emitter zone is defined by the opening 32 'and the opening defined by the blocking mask 35 is identified by 35'. Both of these masks are intentionally not correctly aligned with each other, but this has no effect on the alignment of the emitter zone in the novel method according to the invention. It should also be noted that the emitter mask 32 'overlaps the base mask 43, which shows what tolerances are possible in the mask design with the new method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)

Description

Die Erfindung betrifft ein Verfahren zum Herstellen einer mit einem Störelement dotierten Zone innerhalb eines gewünschten Bereichs der Oberfläche eines Halbleitersubstrats durch Bilden einer aus einer unteren und einer oberen Schicht bestehenden ersten Maskenschicht, deren Materialien selektiv ätzbar sind, und durch Ätzen einer ersten den vorerwähnten Bereich definierenden Öffnung in der ersten Maskenschicht in der Weise, daß ein Teil der oberen Schicht einen Überhang über der unteren Schicht bildet.The invention relates to a method for producing a zone doped with an interference element within a desired region of the surface of a semiconductor substrate by forming a first mask layer consisting of a lower and an upper layer, the materials of which can be selectively etched, and by etching a first defining the aforementioned region Opening in the first mask layer such that part of the upper layer overhangs the lower layer.

Beschreibung des Standes der TechnikDescription of the prior art

Ein Problem, das beim Entwurf von Halbleiterschaltungen eine wesentliche Erhöhung der Anzahl von Transistoren, die innerhalb eines Halbleiterplättchens hergestellt werden können, verhindert hat, ist die Ausrichtung einer mit Störstellen dotierten Zone mit einer anderen ebensolchen Zone. Mit der Verfeinerung der fotografischen und mit Elektronenstrahl arbeitenden lithographischen Verfahren hat man eine wesentliche Verkleinerung der geometrischen Abmessungen der aktiven Zonen oder Bereiche innerhalb eines Halbleiterplättchens erzielen können. Die Schwierigkeiten bei der Ausrichtung von Masken hat jedoch eine volle Ausnutzung der darin liegenden Möglichkeiten verhindert.One problem that has prevented a significant increase in the number of transistors that can be fabricated within a semiconductor die in semiconductor circuit design is the alignment of an impurity-doped zone with another such zone. With the refinement of the photographic and electron beam lithographic processes, it has been possible to achieve a substantial reduction in the geometrical dimensions of the active zones or areas within a semiconductor die. However, the difficulty in aligning masks has prevented the full use of the possibilities therein.

Die heute allgemein gebräuchlichen Verfahren zum Ausrichten benutzen auf der Maske und im darunter liegenden Halbleitersubstrat Ausrichtmarken. Diese Marken werden durch erfahrene Bedienungskräfte von Hand miteinander ausgerichtet. Mit abnehmender Größe der einzelnen Bauelemente und Halbleiterschaltungen nimmt die Möglichkeit von Ausrichtfehlern zu. Auch ist dieses Verfahren wesentlich teuerer, als eine in einem Fertigungsverfahren sich von selbst ergebende Ausrichtung, da nämlich jede Maske für sich ausgerichtet werden muß.Alignment methods commonly used today use alignment marks on the mask and in the underlying semiconductor substrate. These brands are hand-aligned by experienced operators. As the size of the individual components and semiconductor circuits decreases, the possibility of alignment errors increases. This method is also considerably more expensive than an alignment which arises automatically in a production method, since each mask must be aligned individually.

Erst kürzlich ist man beim Entwurf von Halbleiterschaltungen dazu übergegangen, selbstausrichtende Maskenverfahren einzusetzen, wobei dann Sperrmasken benutzt wurden, die die Notwendigkeit einer vollkommenen Maskenausrichtung bei jedem Schritt umgeht. Die US-Patentschriften 3 928 082, 3 948 694, 3 967 981 und die der Anmelderin gehörende US-Patentschrift 3 900 352 sind Beispiele für eine solche, sich von selbst ergebende Ausrichtung. Jedoch ist eine Anwendung dieser Verfahren in der Fertigung entweder durch die erforderliche Ionen-Implantation von einem oder mehreren Störelementen in Bereichen durch eine Maske oder deswegen beschränkt, weil sie sich nur für die Herstellung von auf Abstand liegenden Zonen eignen.Recently, semiconductor circuit design has begun to use self-aligning masking techniques, using blocking masks that circumvent the need for full mask alignment at every step. U.S. Patents 3,928,082, 3,948,694, 3,967,981 and Applicant's U.S. Patent 3,900,352 are examples of such a self-aligning orientation. However, the use of these methods in production is limited either by the required ion implantation of one or more interfering elements in areas through a mask or because they are only suitable for the production of distant zones.

In der FR-A 2 130 397, die der DE-OS 22 12 049 entspricht, ist ein Verfahren zum Ausrichten einer mit Störelementen dotierten Zone innerhalb einer anderen solchen Zone mit Hilfe einer aus zwei in bezug aufeinander selektiv ätzbare Teilschichten bestehende Maskenschicht offenbart, wobei hier die Ausrichtung der beiden Zonen miteinander durch eine durch Unterätzung erzielte Unterschneidung erreicht wird.FR-A 2 130 397, which corresponds to DE-OS 22 12 049, discloses a method for aligning a zone doped with interfering elements within another such zone with the aid of a mask layer consisting of two partial layers which can be selectively etched with respect to one another, whereby here the alignment of the two zones with one another is achieved by an undercut achieved by undercutting.

Eine Schwierigkeit, die bisher beim Entwurf und bei der Herstellung von Halbleiterschaltungen durch bekannte Verfahren nicht richtig erkannt wurde, ist das seitliche Unterschneiden einer Maskenschicht, die während eines Ätzverfahrens unter einer anderen Maskenschicht liegt. Dieses Unterätzen vergrößert die effektive Größe der Öffnung in der Maske für das Eindringen von Störelementen und kann ein Überlappen von Zonen zur Folge haben, die an sich getrennt sein sollten.A difficulty that has not been correctly recognized in the design and manufacture of semiconductor circuits by known methods is the lateral undercutting of a mask layer which lies under another mask layer during an etching process. This under-etching increases the effective size of the opening in the mask for the intrusion of interfering elements and can result in an overlap of zones which should be separate in themselves.

Gesamtdarstellung der Erfindung:Overall presentation of the invention:

Aufgabe der Erfindung ist es daher, ein verbessertes Verfahren zum selbstausrichtenden Eindringen eines Störelementes in a) ein Halbleitersubstrat oder in b) einen anderen mit Störelementen dotierten Bereich innerhalb des Substrats anzugeben. Insbesondere soll es dadurch möglich werden, zwei oder mehr mit Störelementen dotierte Zonen innerhalb eines Substrates oder einer anderen mit Störelementen dotierten Zone herzustellen, wobei diese zwei oder mehr Zonen von selbst miteinander ausgerichtet sind.The object of the invention is therefore to provide an improved method for the self-aligning penetration of an interference element into a) a semiconductor substrate or in b) another region within the substrate doped with interference elements. In particular, this should make it possible to produce two or more zones doped with interference elements within a substrate or another zone doped with interference elements, these two or more zones being automatically aligned with one another.

Diese der Erfindung zugrunde liegende Aufgabe wird dadurch gelöst, daß man die während des Ätzens einer zusammengesetzten Maske aus beispielsweise Siliciumnitrid und Siliciumdioxid sich ergebende Unterschneidung oder Unterätzung mit Vorteil ausnutzt. Im vorliegenden Fall wird diese Unterschneidung oder Unterätzung dazu benutzt sicherzustellen, daß zwischen dem Umfang einer mit Störelementen dotierten Zone und einer anderen, d.h. beispielsweise der Emitter- und der Basiszone eines planaren Transistors ein vorbestimmter kleinster Abstand eingehalten wird.This object of the invention is achieved in that the undercut or undercut resulting from the etching of a composite mask of, for example, silicon nitride and silicon dioxide is advantageously used. In the present case, this undercut or undercut is used to ensure that between the perimeter of a zone doped with interfering elements and another, i.e. For example, the emitter and base zones of a planar transistor are kept at a predetermined minimum distance.

Die Ausgangsposition für die Erfindung besteht zunächst darin daß man auf der Oberfläche eines Substrats eine erste Maskenschicht herstellt, die aus einem unteren und einem oberen Material besteht, die in bezug aufeinander selektiv ätzbar sind, daß anschließend innerhalb der ersten Maskenschicht zunächst eine erste Öffnung in der Weise geätzt wird, daß ein Teil der oberen Schicht am Umfang der ersten Öffnung einen Überhang über der unteren Schicht bildet. Dann wird innerhalb der ersten Öffnung eine zweite Maskenschicht gebildet, die eine Schicht eines Materials einschließt, das mit dem gleichen Ätzmittel ätzbar ist wie die obere Schicht, so daß der Uberhang mindestens teilweise ausgefüllt ist und das gesamte mit dem gleichen Ätzmaterial ätzbare Material innerhalb der Öffnung dünner ist als an ihrem Umfang. Anschließend wird innerhalb der ersten Öffnung mittels einer Sperrmaske durch die zweite Maskenschicht hindurch eine zweite Öffnung geätzt, worauf durch diese zweite Öffnung zur Bildung einer dotieren Zone ein Störelement eingeführt wird.The starting position for the invention consists first of all in that a first mask layer is produced on the surface of a substrate, said mask layer consisting of a lower and an upper material which can be selectively etched with respect to one another, that a first opening in the first mask layer is subsequently provided within the first mask layer It is etched in such a way that part of the upper layer at the periphery of the first opening forms an overhang over the lower layer. A second mask layer is then formed within the first opening, including a layer of material that can be etched with the same etchant is like the upper layer, so that the overhang is at least partially filled and the entire material that can be etched with the same etching material is thinner inside the opening than on its circumference. A second opening is then etched within the first opening by means of a barrier mask through the second mask layer, whereupon an interference element is introduced through this second opening to form a doped zone.

In der bevorzugten Ausführungsform wird die Unterschneidung bis auf etwa 0.7 Micrometer geätzt. Vor Herstellung der zweiten Maskenschicht wird innerhalb der ersten Öffnung eine Basiszone gebildet. Innerhalb der zweiten Öffnung wird dann eine Emitterzone gebildet. Wenn alles in dieser Weise ausgeführt wird, so erhält man einen Abstand zwischen dem Umfang der Emitterzone und dem Umfang der Basiszone von etwa 0.7 Micrometer, so daß auf diese Weise eine selbsttätige Ausrichtung sichergestellt ist.In the preferred embodiment, the undercut is etched down to about 0.7 microns. Before the second mask layer is produced, a base zone is formed within the first opening. An emitter zone is then formed within the second opening. If everything is carried out in this way, a distance between the circumference of the emitter zone and the circumference of the base zone of approximately 0.7 micrometers is obtained, so that an automatic alignment is ensured in this way.

Ein vorteilhaftes weiteres Merkmal der Erfindung besteht darin, daß innerhalb der Basiszone mehr als eine Zone gebildet werden kann. Beispielsweise können Emitter- und Basiskontakte lediglich durch Verwendung einer Sperrmaske mit selbsttätiger Ausrichtung hergestellt werden.An advantageous further feature of the invention is that more than one zone can be formed within the base zone. For example, emitter and base contacts can only be made by using a blocking mask with automatic alignment.

Die Erfindung wird nunmehr anhand eines Ausführungsbeispiels in Verbindung mit den beigefügten Zeichnungen im einzelnen beschrieben.The invention will now be described in detail using an exemplary embodiment in conjunction with the accompanying drawings.

In den Zeichnungen zeigen

  • Fign. 1 A-1 Querschnittsansichten eines Halbleiterbauelementes bei verschiedenen Fertigungsstufen mit einem Verfahren gemäß der Erfindung,
  • Fig. 2 eine Draufsicht auf ein Halbleiterbauelement, bie der in Fig. 1 dargestellten Verfahrensstufe.
Show in the drawings
  • Fig. 1A-1 cross-sectional views of a semiconductor device at various manufacturing stages using a method according to the invention,
  • Fig. 2 is a plan view of a semiconductor device, the process stage shown in Fig. 1.

Insbesondere zeigt Fig. 1 A einen teilweise fertiggestellten bipolaren Transistor, der nach bisher üblichen Verfahren hergestellt worden ist. Eine N+-leitende vergrabene Schicht 7 liegt teilweise in einem P-leitenden Halbleitersubstrat 2 und teilweise innerhalb einer N-leitenden epitaxialen Schicht 6. Diese Subkollektorzone wird normalerweise dadurch hergestellt, daß man zunächst Arsen als Störelement in das Substrat 2 eindiffundiert und anschließend eine N-leitenc!2. Epitaxialschicht 6 bis zu einer Dicke von etwa 2.0 Micrometern darauf aufwachsen läßt.In particular, FIG. 1A shows a partially completed bipolar transistor, which has been manufactured by previously customary methods. An N + -type buried layer 7 lies partly in a P-type semiconductor substrate 2 and partly within an N-type epitaxial layer 6. This subcollector zone is normally produced by first diffusing arsenic into the substrate 2 as an interfering element and then an N -leitenc! 2. Epitaxial layer 6 can grow thereon up to a thickness of about 2.0 micrometers.

Das Substrat enthält ferner eine P+-leitende Isolationsdiffusion 4, die die Subkollektorzone 7 umgibt. Die P+-leitende Isolationsdiffusion 4 wird gewöhnlich dadurch hergestellt, daß man vor dem epitaxialen Niederschlag Bor als Störelement in den Halbleiterkörper 2 eindiffundiert, so daß bei der nachfolgenden Herstellung der Epitaxialschicht die P+-leitende Isolationsdiffusion durch Ausdiffusion in die Epitaxialschicht 6 eindringt. Wie bereits erwähnt, sind die Verfahren zum Herstellen der Subkollektorzone und der Isolationsdiffusionszone dem Fachmann allgemein bekannt und lassen sich auf verschiedene Weise durchführen. Die Dicke der Epitaxialschicht 6 kann geringer oder größer sein als 2.0 Micrometer.The substrate also contains a P + - conductive insulation diffusion 4 which surrounds the sub-collector zone 7. The P + - conductive insulation diffusion 4 is usually produced by diffusing boron as a disturbing element into the semiconductor body 2 before the epitaxial precipitation, so that in the subsequent production of the epitaxial layer the P + - conductive insulation diffusion penetrates into the epitaxial layer 6 by diffusion. As already mentioned, the methods for producing the sub-collector zone and the insulation diffusion zone are generally known to the person skilled in the art and can be carried out in various ways. The thickness of the epitaxial layer 6 can be less than or greater than 2.0 micrometers.

Auf der Epitaxialschicht 6 sind drei Maskenschichten 8, 10 und 12 angebracht, die vorzugweise aus Siliciumdioxid, Siliciumnitrid bzw. Siliciumdioxid in dieser Reihenfolge bestehen. Die Maskenschicht 8 wird thermisch auf der Epitaxialschicht 6 bis zu einer Dicke von etwa 140 bis 200 nm aufgewachsen. Die Siliciumnitridschicht 10 kann durch chemischen Niederschlag aus der Dampfphase bis zu einer Dicke zwischen 50 und 150 nm niedergeschlagen werden. Die Maskenschicht 10 kann stattdessen auch aus Silicium-Oxinitrid bestehen. Die Maskenschicht 12 besteht aus chemisch aus der Dampfphase niedergeschlagenem Siliciumdioxid. Diese Siliciumdioxidschicht 12 hat lediglich die Aufgabe, die Nitridschicht 10 zu maskieren, da Ätzmittel, wie zum Beispiel heiße Phosphorsäure, die Siliciumnitrid angreift, auch normale Fotolacke angreift. Anstelle der durch chemischen Niederschlag aus der Dampfphase aufgebrachten Schicht 12 kann diese durch eine durch Kathodenzerstäubung aufgebrachte Siliciumoxidschicht oder andere bekannte Masken ersetzt werden. Andererseits kann die Maskenschicht 12 auch ganz weggelassen werden, wenn das Ätzen als Plasmaätzen durchgeführt wird. Diese Art von Ätzen wird allgemein als reaktives lonen- oder Plasmaätzen bezeichnet. Beispielsweise läßt sich die Nitridschicht 10 unter Verwendung einer Mischung aus gasförmigem CF4 und O2 in einem Plasmasystem ätzen, indem man den AZ1350H-Fotolack als eine Maske benutzt.On the epitaxial layer 6, three mask layers 8, 10 and 12 are applied, which preferably consist of silicon dioxide, silicon nitride or silicon dioxide in this order. The mask layer 8 is thermally grown on the epitaxial layer 6 to a thickness of approximately 140 to 200 nm. The silicon nitride layer 10 can be deposited by chemical precipitation from the vapor phase to a thickness between 50 and 150 nm. Instead, the mask layer 10 can also consist of silicon oxynitride. The mask layer 12 consists of silicon dioxide chemically deposited from the vapor phase. This silicon dioxide layer 12 only has the task of masking the nitride layer 10, since etching agents, such as hot phosphoric acid, which attack the silicon nitride, also attack normal photoresists. Instead of the layer 12 applied by chemical precipitation from the vapor phase, this can be replaced by a silicon oxide layer applied by cathode sputtering or other known masks. On the other hand, the mask layer 12 can also be omitted entirely if the etching is carried out as plasma etching. This type of etching is commonly referred to as reactive ion or plasma etching. For example, the nitride layer 10 can be etched using a mixture of gaseous CF 4 and O 2 in a plasma system using the AZ1350H photoresist as a mask.

Gemäß Fig. 1 B werden unter Verwendung einer Maske, die die verschiedenen Zonen in dem Transistor begrenzt, Öffnungen in die Siliciumdioxidschicht 12 geätzt. In der Darstellung werden die Basiszone, die Anschlußzone für die Subkollektorzone und die Isolationszonen durch die Maske definiert. Andere Zonen, wei zum Beispiel Schottky-Sperrschichtdioden und Widerstände können durch die, gleiche Maske an benachbarten Stellen in der Epitaxialschicht 6 definiert werden. Die Schottky-Sperrschichtdiode und der Widerstand, die mit dem Transistor gemeinsam hergestellt werden können, sind nicht gezeigt. Ihre Herstellung läuft jedoch mit den gleichen Verfahrensschritten ab, wie die Bildung der Anschlußzone 11 für den Subkollektor, die beschrieben werden wird.1B, openings are etched into the silicon dioxide layer 12 using a mask that delimits the various zones in the transistor. In the illustration, the base zone, the connection zone for the sub-collector zone and the isolation zones are defined by the mask. Other zones, for example Schottky junction diodes and resistors, can be defined by the same mask at adjacent locations in the epitaxial layer 6. The Schottky junction diode and resistor that can be fabricated with the transistor are not shown. However, their manufacture follows the same process steps as the formation of the connection zone 11 for the sub-collector, which will be described.

Die die Dimensionen festlegende Maske, die die verschiedenen Zonen begrenzt, besteht im allgemeinen aus einem Fotolack, wie zum Beispiel AZ1350J der Firma Shipley, der in der üblichen Weise belichtet und entwickelt wird. Die pyrolitisch niedergeschlagene Siliciumdioxidschicht 12 kann mittels einer Lösung einer in Ammoniumfluorid gepufferten Flußsäure geätzt werden, wobei dieses Ätzmittel Siliciumnitrid im wesentlichen nicht angreift. Die in den Öffnungen der Siliciumdioxidschicht 12 freiliegenden Bereiche der Nitridschicht 10 werden dann in heißer Phosphorsäure oder in jedem anderen Ätzmittel abgeätzt, das Siliciumdioxid nicht angreift. Während dieses Ätzverfahrensschrittes werden die den Subkollektor und die Isolationszone trennenden Bereiche durch den Fotolack maskiert. Somit werden bei diesem Verfahrensschritt bestimmte Zonen in der Siliciumdioxidshicht 12 definiert.The mask defining the dimensions, which delimits the different zones, generally consists of a photoresist, such as AZ1350J from Shipley, which is exposed and developed in the usual way. The pyrolytically deposited silicon dioxide layer 12 can be etched by means of a solution of a hydrofluoric acid buffered in ammonium fluoride, this etchant silicon nitride in the essentially does not attack. The areas of the nitride layer 10 exposed in the openings of the silicon dioxide layer 12 are then etched off in hot phosphoric acid or in any other etchant which does not attack the silicon dioxide. During this etching step, the areas separating the sub-collector and the isolation zone are masked by the photoresist. Certain zones are thus defined in the silicon dioxide layer 12 in this method step.

Anschließend wird eine aus Fotolack bestehende Sperrmaske zum Herstellen einer Öffnung für den Subkollektor anschluß sowie einer Öffnung für den Widerstandsbereich (nicht gezeigt) benutzt. Die Lage der Subkollektorzone und der Widerstandsbereiche wird ferner dadurch definiert, daß man die freiliegenden Bereiche der Siliziumnitridschicht 10 in heißer Phosphorsäure oder jedem anderen Ätzmittel ätzt, das Siliciumdioxid nicht angreift. Nachdem diese Öffnungen in der Siliciumnitridschicht 10 hergestellt sind, wird das Halbleiterplättchen einem Ätzmittel ausgesetzt, das die Bereiche der Oxidschicht 8 angreift, die in den Öffnungen der Siliciumnitridschicht 10 freiliegen. Zum Ätzen der Siliciumdioxidschicht 8 wird vorzugsweise in Ammoniumfluorid gepufferte Flußsäure benutzt. Andere Zonen der Siliciumnitridschicht 10 und der Siliciumdioxidschicht 8 sind durch die aus Fotolack bestehende Sperrmaske geschützt und werden nicht angegriffen. Dann wird die Fotolackschicht vollständig abgezogen und es wird durch die Öffnung zur Bildung der durchgehenden Verbindung 11 nach dem Subkollektor eine Diffusion durchgeführt. Der Dotierungsstoff für den Subkollektor ist gewöhnlich Phosphor, obgleich auch Arsen oder ein anderes Störelement der Gruppe V verwendet werden kann. Der Phosphor wird bei einer Temperatur von 1000°C in einer oxidierenden Atmosphäre eingetrieben, wodurch eine Oxidschicht bis zu einer Dicke von etwa 140 nm aufwächst, wie dies Fig. 1D zeigt. Zu diesem Zeitpunkt ist die pyrolitisch niedergeschlagene Oxidschicht 12 abgezogen und der N+-leitende Anschlußbereich 11 für die Subkollektorzone und der zusätzliche Widerstandsbereich (nicht gezeigt) sind fertiggestellt. Das Substrat ist dabei vollstädig mit einer thermisch aufgewachsenen Siliciumdioxidschicht 8 überzogen und die verbleibenden, noch herzustellenden Zonen sind durch die Siliciumnitridschicht 10 definiert.Then a blocking mask consisting of photoresist is used to produce an opening for the sub-collector connection and an opening for the resistance region (not shown). The location of the sub-collector zone and the resistance areas is further defined by etching the exposed areas of the silicon nitride layer 10 in hot phosphoric acid or any other etchant that does not attack silicon dioxide. After these openings are made in the silicon nitride layer 10, the semiconductor die is exposed to an etchant which attacks the regions of the oxide layer 8 which are exposed in the openings of the silicon nitride layer 10. Hydrofluoric acid buffered in ammonium fluoride is preferably used to etch the silicon dioxide layer 8. Other zones of the silicon nitride layer 10 and the silicon dioxide layer 8 are protected by the barrier mask consisting of photoresist and are not attacked. Then the photoresist layer is completely stripped off and diffusion is carried out through the opening to form the continuous connection 11 after the sub-collector. The dopant for the sub-collector is usually phosphorus, although arsenic or another Group V interfering element can also be used. The phosphorus is driven in at a temperature of 1000 ° C. in an oxidizing atmosphere, as a result of which an oxide layer grows to a thickness of approximately 140 nm, as shown in FIG. 1D. At this point, the pyrolytically deposited oxide layer 12 has been stripped off and the N + -type connection region 11 for the sub-collector zone and the additional resistance region (not shown) have been completed. The substrate is completely covered with a thermally grown silicon dioxide layer 8 and the remaining zones still to be produced are defined by the silicon nitride layer 10.

Bei diesem Stand des Verfahrens wird durch die Siliciumdioxidschicht 8 hindurch eine Öffnung nach der P+-leitenden Zone 17 hergestellt. Die thermisch aufgewachsene Siliciumdioxidschicht über der N-leitenden Zone 14, die durchgehende Anschlußzone 11 und der Widerstandsbereich sind durch die Sperrmaske 18 geschützt. Anschließend wird eine Diffusion von P-leitendem Material, etwa Bor, in dem freiliegenden Bereich durchgeführt, wodurch die P+- leitende Isolationszone 17 gemaß Fig. 1 E gebildet wird.In this state of the method, an opening is made through the silicon dioxide layer 8 after the P + - conducting zone 17. The thermally grown silicon dioxide layer over the N-conductive zone 14, the continuous connection zone 11 and the resistance area are protected by the barrier mask 18. A diffusion of P-conductive material, such as boron, is then carried out in the exposed area, as a result of which the P + -conductive insulation zone 17 according to FIG. 1E is formed.

Im nächsten, in Fig. 1 F dargestellten Verfahrensschritt wird eine andere Sperrmaske 22 zum Schutz aller Bereiche des Substrats mit Ausnahme der Zone 14 eingesetzt. Dann wird in der Siliciumdioxidschicht 8 eine Öffnung zum Freilegen der Zone 14 hergestellt. Dieses Ätzverfahren ergibt eine Unterschneidung der Siliciumnitridschicht 10 in den Bereichen 15, d. h. daß ein schmales aus Siliciumdioxid bestehende Band unter der Siliciumnitridschicht entfernt wird, so daß ein Überhang entsteht. Diese Unterschneidung ist für die vorliegende Erfindung kritisch und muß genau überwacht werden, wenn die Siliciumdioxidschicht 8 in gepufferter Flußsäure geätzt wird. Die Ätzgeschwindigkeit von thermisch aufgewachsenem Siliciumdioxid in 7:1 gepufferter Flußsäure bei 31°C beträgt etwa 160 nm je Minute. Wenn daher die Öffnungen nach der Zone 14 hergestellt sind, dann wird das Ätzen bis zum Erzielen einer Unterschneidung von etwa 0.6 bis 0.7 Micrometern fortgesetzt. Andererseits könnte das Ätzen auch mittels einer Plasmaätzung für eine genau überwachte Unterschneidung durchgeführt werden.In the next process step, shown in FIG. 1F, another barrier mask 22 is used to protect all areas of the substrate with the exception of zone 14. Then an opening is made in the silicon dioxide layer 8 to expose the zone 14. This etching process results in an undercut of the silicon nitride layer 10 in the regions 15, i. H. that a narrow band of silicon dioxide is removed from under the silicon nitride layer so that an overhang arises. This undercut is critical to the present invention and must be closely monitored when the silicon dioxide layer 8 is etched in buffered hydrofluoric acid. The etching rate of thermally grown silicon dioxide in 7: 1 buffered hydrofluoric acid at 31 ° C is about 160 nm per minute. Therefore, when the openings are made after zone 14, the etching is continued until an undercut of about 0.6 to 0.7 micrometers is achieved. On the other hand, the etching could also be carried out by means of a plasma etching for a precisely monitored undercut.

Dann wird die P-leitende Basiszone 24 in die N--leitende Epitaxialzone 6 eindiffundiert. Die Basiszone kann auch durch Ionen-Implantation und anschließendes Eintreiben hergestellt werden, wobei man im wesentlichen die gleiche Art von Basiszone erhält. Somit ist die Diffusionsöffnung, die durch die thermisch aufgewachsene Siliciumdioxidschicht 8 definiert, ist, auf jeder Seite um mindestens 0.6 bis 0.7 Micrometer weiter, als die in der Siliciumnitridschicht 10 gebildete Öffnung.Then the P-type base zone 24 is diffused into the N-type epitaxial zone 6. The base zone can also be fabricated by ion implantation and subsequent driving, giving essentially the same type of base zone. Thus, the diffusion opening defined by the thermally grown silicon dioxide layer 8 is wider on each side by at least 0.6 to 0.7 microns than the opening formed in the silicon nitride layer 10.

Bei einem typischen Basis-Diffusionsverfahren wird BBr3 in einer aus trockenem Sauerstoff und Argon bestehenden Atmosphäre bei etwa 875°C als Borsilikatglas bis zu einer Dicke von etwa 40 nm niedergeschlagen. Nach der Diffusion wird das Glas zur Entfernung der gesamten Glasschicht in gepufferter Flußsäure abgeätzt und die Basis wird durch übliches Eintreiben und ein Reoxidationsverfahren gebildet, das bei 925°C in Wasserdampf und Sauerstoff abläuft. Dadurch bildet sich eine Schicht 26 aus thermisch aufgewachsenem Siliciumoxid mit einer Stärke von 80 nm über der Basiszone und den Isolationsbereichen, wie dies Fig. 1 G zeigt. Die Oxidschicht 26 bildet sich außerdem unter dem aus Siliciumnitrid bestehenden Überhang.In a typical basic diffusion process, BBr 3 is deposited in a dry oxygen and argon atmosphere at about 875 ° C as borosilicate glass to a thickness of about 40 nm. After the diffusion, the glass is etched in buffered hydrofluoric acid to remove the entire glass layer and the base is formed by conventional driving in and a reoxidation process which takes place at 925 ° C. in water vapor and oxygen. This forms a layer 26 of thermally grown silicon oxide with a thickness of 80 nm above the base zone and the insulation regions, as shown in FIG. 1G. The oxide layer 26 also forms under the overhang made of silicon nitride.

Zu diesem Zeitpunkt sei darauf hingewiesen, daß die P-leitenden Zonen 17 und 24 gleichzeitig gebildet werden können, was natürlich von den Verfahrenparametern abhängt.At this point it should be noted that P-type zones 17 and 24 can be formed simultaneously, which of course depends on the process parameters.

In dem nächsten in Fig. 1 H dargestellten Verfahrensschritt werden nacheinander Schichten aus Siliciumnitrid und Siliciumdioxid, die mit 28 bzw. 30 bezeichnet sind, enteder durch chemischen Neiderschlag aus der Dampfphase oder durch Kathodenzerstäubung aufgebracht. Die Dicke der Schicht 28 und 30 beträgt vorzugsweise etwa 100 nm. Die Schicht 30 dient während eines Naßätzverfahrens mit heißer Phosphorsäure lediglich als Maske. für die Siliciumnitridschicht 28. Durch diesen Neiderschlag wird der Überhang unterhalb der Siliciumnitridschicht an der Unterschneidungszone 15 vollständig ausgefüllt. Die Zusammensetzung und Dicke der hier niedergeschlagenen Materialien kann dabei anders sein. Beispielsweise könnte, was jedoch weniger wünschenswert ist, die Basisoxidschicht 26 dicker gemacht werden, so daß dadurch die Unterschneidungszone 15 vollständig ausgefüllt wird, ohne daß dafür noch Siliciumnitrid benötigt würde. Ferner könnte Siliciumnitrid durch Silicium-Oxinitrid oder ein anderes Maskenmaterial ersetzt werden. In der Tat könnte die Schicht 28 aus Silicium-Oxinitrid und die Schicht 10 aus Siliciumnitrid bestehen oder umgekehrt. Die wichtige Überlegung hierbei ist, daß die Dicke der Maskenschicht am Umfang der Basisöffnung größer ist, als die Dicke der Maskenschicht innerhalb der Öffnung, wobei beide mit dem gleichen Ätzmittel ätzbar sind. Auf diese Weise können Sperrmasken für die Definition der Emitterzone und anderer mit Störelementen dotierter Zonen verwendet werden, ohne die Schwierigkeit, bis auf die geschützten Flächen des Substrats hinab ätzen zu müssen. Anschließend wird eine einzelne Maske 29 zur Bildung von Öffnungen auf der Oxidschicht 30 hergestelt zur Bildung des Basiskontakts und der Emitterzonen über der Basiszone 24. Die hier dargestellte Ausführungsform zeigt eine einzige für Basiskontakt bestimmte Öffnung. Es können aber auch zwei oder mehrere Kontakte auf jeder Seite des Emitters gebildet werden. Die Breite des Emitters innerhalb der Basiszone 24 wird durch das neue Verfahren sorgfältig gesteuert. Dies VIt:rd durch die vollkommen ausgefüllte Unterschneidung 15 und die doppelten Maskenschichten am Umfang der Basisöffnung ermöglicht. Da dadurch die Emmitteröffnung ganz exakt definiert ist, verhindert diese doppelte Maskenschicht, daß der Emitter zu nahe in Richtung auf den Umfang der Basiszone 24 nach der Seite diffundiert. Wie Fig. 11 zeigt, wird die Siliciumdioxidschicht 30 dann zum Herstellen der öffnungen 31, 32 und 33 durch die Sperrmaske 29 hindurch geätzt. Ebenso wird das Siliciumnitrid an den freiliegenden Bereichen abgeätzt, wobei die Siliciumdioxidschicht 30 als eine Maske benutzt wird.In the next process step shown in FIG. 1H, layers of silicon nitride and silicon dioxide, which are denoted by 28 and 30 respectively, are sequentially removed by chemical jealousy from the vapor phase or applied by sputtering. The thickness of layers 28 and 30 is preferably approximately 100 nm. Layer 30 serves only as a mask during a wet etching process with hot phosphoric acid. for the silicon nitride layer 28. This overlap completely fills up the overhang below the silicon nitride layer at the undercut zone 15. The composition and thickness of the materials deposited here can be different. For example, what is less desirable, the base oxide layer 26 could be made thicker so that the undercut zone 15 is completely filled without the need for silicon nitride. Furthermore, silicon nitride could be replaced by silicon oxynitride or another mask material. Indeed, layer 28 could be silicon oxynitride and layer 10 silicon nitride, or vice versa. The important consideration here is that the thickness of the mask layer at the periphery of the base opening is greater than the thickness of the mask layer inside the opening, both of which can be etched with the same etchant. In this way, blocking masks can be used to define the emitter zone and other zones doped with interfering elements without the difficulty of etching down to the protected areas of the substrate. A single mask 29 is then fabricated to form openings on the oxide layer 30 to form the base contact and the emitter zones above the base zone 24. The embodiment shown here shows a single opening intended for base contact. However, two or more contacts can also be formed on each side of the emitter. The width of the emitter within the base zone 24 is carefully controlled by the new method. This is made possible by the completely filled undercut 15 and the double mask layers on the circumference of the base opening. Since this defines the emitter opening exactly, this double mask layer prevents the emitter from diffusing too close towards the circumference of the base zone 24 to the side. 11 shows, the silicon dioxide layer 30 is then etched through the barrier mask 29 to produce the openings 31, 32 and 33. Likewise, the silicon nitride is etched away at the exposed areas, using the silicon dioxide layer 30 as a mask.

Eine zweite Sperrmaske 35, die die Zone 31 gegen Ätzen schützt, wird dann zum Abätzen der thermisch aufgewachsenen Siliciumdioxidschicht 26 in den in Fig. 1 gezeigten Öffnungen 32 und 33 benutzt. Zum Freilegen der Öffnungen 32' und 33' bis zur Oberfläche der Schicht 6 wird ein übliches Ätzverfahren mit gepufferter Flußsäure oder Plasmaätzen eingesetzt. Die Emmiterzone wird dann in üblicher Weise, beispielsweise durch die Diffusion von Arsen gebildet. In gleicher Weise wird die Leitfähigkeit in dem Verbindungsbereich 11 durch Arsendiffusion im Bereich 40 erhöht.A second barrier mask 35, which protects the zone 31 against etching, is then used to etch the thermally grown silicon dioxide layer 26 in the openings 32 and 33 shown in FIG. 1. A conventional etching method using buffered hydrofluoric acid or plasma etching is used to expose the openings 32 'and 33' to the surface of the layer 6. The emitter zone is then formed in the usual way, for example by the diffusion of arsenic. In the same way, the conductivity in the connection area 11 is increased by arsenic diffusion in the area 40.

Eine Öffnung für eine Schottky-Sperrschichtdiode kann während dieses Verfahrensschritts bis zur epitaxialen Schicht 6 hinunter in einem Bereich, der hier nicht gezeigt ist, hergestellt werden.An opening for a Schottky junction diode can be made during this process step down to the epitaxial layer 6 in an area that is not shown here.

Der Kontakt mit der Basiszone kann dadurch hergestellt werden, daß man die Öffnungen 32 und 33 mit einer Sperrmaske verschließt, während der innerhalb der Öffnung 31 freiliegende Teil der Siliciumdioxidschicht 26 frei bleibt. Es kann hierbei erwünscht sein, eine dünne abschirmende Oxidschicht mit einer Stärke von etwa 10 nm im Bereich von Emitter-und Subkollektorzonen niederzuschlagen, um dadurch diese Zonen gegen eine Verunreinigung durch den Fotolak zu schützen. Dann wird das Oxid in der Öffnung 31 entfernt, wodurch der Basiskontaktbereich für eine nachfolgende Metallisierung (nicht gezeigt) freigelegt wird.Contact with the base zone can be made by closing openings 32 and 33 with a barrier mask while leaving the portion of silicon dioxide layer 26 exposed within opening 31 free. It may be desirable to deposit a thin shielding oxide layer with a thickness of approximately 10 nm in the area of the emitter and subcollector zones, in order to thereby protect these zones against contamination by the photoresist. The oxide in opening 31 is then removed, exposing the base contact area for subsequent metallization (not shown).

In Fig. 2 ist eine Draufsicht auf den Transistor bei dem in Fig. 1 dargestellten Verfahrensstand gezeigt, wobei die automatische Ausrichtung der Emmitterzone 36 innerhalb der Basiszone 24 zu erkennen ist. Dabei wird immer wegen der zuvor besprochenen Unterschneidung ein ausgewählter Abstand zwischen der Kante der Emitterzone 36 und der Kante der Basiszone 34 vorhanden sein. Beim derzeitigen Stand der Technik ist diese Unterschneidung mindestens 0.7 Micrometer breit.FIG. 2 shows a top view of the transistor in the process state shown in FIG. 1, wherein the automatic alignment of the emitter zone 36 within the base zone 24 can be seen. Because of the undercut previously discussed, there will always be a selected distance between the edge of the emitter zone 36 and the edge of the base zone 34. In the current state of the art, this undercut is at least 0.7 microns wide.

Die durch die Siliciumnitridschicht 10 definierte Maske für die Basiszone und die durch die Oxidschicht 8 in Fig. 1 F definierte Öffnung für die Basisdiffusion sind durch die Bezugszeichen 43 und 44 bezeichnet. Die Maske für die Emmiterzone ist durch die Öffnung 32' definiert und die durch die Sperrmaske 35 definierte Offnung ist durch 35' gekennzeichnet. Dabei sind beide dieser Masken absichtlich nicht richtig miteinander ausgerichtet dargestellt, doch hat dies bei dem neuartigen Verfahren gemäß der Erfindung keine Auswirkung auf die Ausrichtung der Emitterzone. Es sei weiter darauf hingewiesen, daß die Emittermaske 32' die Basismaske 43 überlappt, was zeigt,, welche Toleranzen bei der Maskengestaltung bei dem neuen Verfahren möglich sind.The mask for the base zone defined by the silicon nitride layer 10 and the opening for the base diffusion defined by the oxide layer 8 in FIG. 1F are designated by the reference numerals 43 and 44. The mask for the emitter zone is defined by the opening 32 'and the opening defined by the blocking mask 35 is identified by 35'. Both of these masks are intentionally not correctly aligned with each other, but this has no effect on the alignment of the emitter zone in the novel method according to the invention. It should also be noted that the emitter mask 32 'overlaps the base mask 43, which shows what tolerances are possible in the mask design with the new method.

Claims (9)

1. Method of making a region doped with an impurity within a predetermined region of the surface of a semiconductor substrate, by forming a first masking layer (8, 10) consisting of a lower (8) and an upper (10) layer whose materials are selectively etchable, and by etching a first window defining the above mentioned area in the first masking layer in such a manner that a portion of the upper layer (10) forms an overhang (15) over the lower layer (8), characterized by the following further process steps: forming a second masking layer (26, 28) which includes a layer of a material which is etchable with the same etchant as the upper layer (10) so that the overhang is filled in at least partly, and the entire material mentioned above etchable with the same etchant is thinner within the window than at its periphery, etching a second window (32) within the first window through the second masking layer (26, 28) by means of a blocking mask, and introducing an impurity through the second window to form the impurity region (36).
2. Method as claimed in claim 1, characterized in that during the forming of the region (36) doped with an impurity another impurity-doped region (40) of the same conductivity is formed in a region of the substrate outside the first window.
3. Method as claimed in claim 1, characterized, in that in the forming of the second masking layer (26, 28) the overhang (15) is filled in by the lower layer exclusively.
4. Method as claimed in claim 1, characterized in that in the forming of the second masking layer the overhang is filled in by the lower and the upper layer (26, 28).
5. Method as claimed in claims 1 to 4, characterized in that as material for the lower layer (8) of the first masking layer silicon dioxide is used, and as material for the upper layer (10) silicon nitride or silicon oxynitride is used.
6. Method as claimed in claims 1 to 4, characterized in that in the second masking layer for the material etchable with the same etchant silicon nitride or silicon oxynitride is used.
7. Method as claimed in claim 1, characterized in that in the forming of the second masking layer a silicon dioxide layer (26) is thermally grown on the exposed substrate surface, said layer partially filling in the overhang (15).
8. Method as claimed in claim 1, characterized in that as a material for the lower layer (8) of the first masking layer silicon dioxide is used, and as material for the upper layer (10) silicon nitride is used, and that as materials for the second masking layer a lower silicon dioxide layer and an upper silicon nitride layer is used.
9. Method as claimed in claim 8, characterized in that for defining a second region within the first window during etching of the second window through the silicon nitride layer a third window is etched through the silicon nitride layer while protecting other portions of the masking layer, that after the etching of the silicon dioxide layer the third window is made by etching the silicon dioxide layer in the second window while simultaneously protecting against etching other portions of the masking layers, and the second window.
EP78100081A 1977-07-12 1978-06-02 Method of forming very small impurity regions in a semiconductor substrate Expired EP0000326B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US814829 1977-07-12
US05/814,829 US4131497A (en) 1977-07-12 1977-07-12 Method of manufacturing self-aligned semiconductor devices

Publications (2)

Publication Number Publication Date
EP0000326A1 EP0000326A1 (en) 1979-01-24
EP0000326B1 true EP0000326B1 (en) 1980-09-17

Family

ID=25216103

Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100081A Expired EP0000326B1 (en) 1977-07-12 1978-06-02 Method of forming very small impurity regions in a semiconductor substrate

Country Status (4)

Country Link
US (1) US4131497A (en)
EP (1) EP0000326B1 (en)
JP (1) JPS5419677A (en)
DE (1) DE2860161D1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4210689A (en) * 1977-12-26 1980-07-01 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing semiconductor devices
US4263057A (en) * 1978-04-19 1981-04-21 Rca Corporation Method of manufacturing short channel MOS devices
US4199380A (en) * 1978-11-13 1980-04-22 Motorola, Inc. Integrated circuit method
FR2454698A1 (en) * 1979-04-20 1980-11-14 Radiotechnique Compelec METHOD FOR PRODUCING INTEGRATED CIRCUITS USING A MULTILAYER MASK AND DEVICES OBTAINED BY THIS METHOD
US4243435A (en) * 1979-06-22 1981-01-06 International Business Machines Corporation Bipolar transistor fabrication process with an ion implanted emitter
US4272882A (en) * 1980-05-08 1981-06-16 Rca Corporation Method of laying out an integrated circuit with specific alignment of the collector contact with the emitter region
EP0054303B1 (en) * 1980-12-17 1986-06-11 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
JPH084780Y2 (en) * 1986-04-01 1996-02-07 三洋電機株式会社 Electronic viewfinder mounting mechanism
JPH0249280U (en) * 1988-09-30 1990-04-05
US5079177A (en) * 1989-09-19 1992-01-07 National Semiconductor Corporation Process for fabricating high performance bicmos circuits
JP2509717B2 (en) * 1989-12-06 1996-06-26 株式会社東芝 Method for manufacturing semiconductor device
US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
KR102013416B1 (en) * 2012-10-26 2019-08-22 어플라이드 머티어리얼스, 인코포레이티드 Combinatorial masking

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967981A (en) * 1971-01-14 1976-07-06 Shumpei Yamazaki Method for manufacturing a semiconductor field effort transistor
NL173110C (en) * 1971-03-17 1983-12-01 Philips Nv METHOD FOR MANUFACTURING A SEMI-CONDUCTOR DEVICE APPLICATING ON A SURFACE OF A SEMI-CONDUCTOR BODY AT LEAST TWO PART-LAYERS OF DIFFERENT MATERIAL COATING.
US4028150A (en) * 1973-05-03 1977-06-07 Ibm Corporation Method for making reliable MOSFET device
US3900352A (en) * 1973-11-01 1975-08-19 Ibm Isolated fixed and variable threshold field effect transistor fabrication technique
US3928082A (en) * 1973-12-28 1975-12-23 Texas Instruments Inc Self-aligned transistor process
US3951693A (en) * 1974-01-17 1976-04-20 Motorola, Inc. Ion-implanted self-aligned transistor device including the fabrication method therefor
US3948694A (en) * 1975-04-30 1976-04-06 Motorola, Inc. Self-aligned method for integrated circuit manufacture
US3961999A (en) * 1975-06-30 1976-06-08 Ibm Corporation Method for forming recessed dielectric isolation with a minimized "bird's beak" problem
JPS5223263A (en) * 1975-08-18 1977-02-22 Nec Corp Method of manufacturing semiconductor device
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap
US4060427A (en) * 1976-04-05 1977-11-29 Ibm Corporation Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
US4052229A (en) * 1976-06-25 1977-10-04 Intel Corporation Process for preparing a substrate for mos devices of different thresholds
US4040891A (en) * 1976-06-30 1977-08-09 Ibm Corporation Etching process utilizing the same positive photoresist layer for two etching steps
US4061530A (en) * 1976-07-19 1977-12-06 Fairchild Camera And Instrument Corporation Process for producing successive stages of a charge coupled device

Also Published As

Publication number Publication date
US4131497A (en) 1978-12-26
JPS5419677A (en) 1979-02-14
JPS6138623B2 (en) 1986-08-30
DE2860161D1 (en) 1980-12-18
EP0000326A1 (en) 1979-01-24

Similar Documents

Publication Publication Date Title
DE3689158T2 (en) Methods of manufacturing card-implanted areas and electrodes therefor.
DE2745857C2 (en)
EP0000327B1 (en) Method for making self-aligned integrated semiconductor devices
DE2818090C2 (en)
EP0036634B1 (en) Method of making a bipolar transistor structure
DE2628407A1 (en) PROCESS FOR PRODUCING BURIED DIELECTRIC INSULATION
EP0032999A2 (en) Process for producing a bipolar vertical transistor structure
DE2707693C3 (en) Method for producing doped zones of a specific type of conduction in a semiconductor substrate by means of ion implantation
DE2626738C2 (en) Process for the formation of recessed dielectric isolation zones in monolithically integrated semiconductor circuits
EP0000326B1 (en) Method of forming very small impurity regions in a semiconductor substrate
EP0020998B1 (en) Process for making a bipolar transistor with an ion-implanted emitter
EP0006510B1 (en) Method of forming adjacent impurity regions of different doping in a silicon substrate
EP0182088B1 (en) Schottky contact on a semiconductor surface and method of making the same
EP0030640A2 (en) Process for putting a self-aligning gate electrode in a V-MOS field-effect transistor
DE3245064A1 (en) METHOD FOR ATTACHING A NARROW NUT OR GAP IN A SUBSTRATE AREA, IN PARTICULAR A SEMICONDUCTOR SUBSTRATE AREA
DE2618445A1 (en) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
DE19837395A1 (en) Method for producing a semiconductor insulation layer and a semiconductor component containing this semiconductor insulation layer
DE2729973C2 (en) Method for producing a semiconductor device
DE3825701A1 (en) METHOD FOR PRODUCING A BIPOLAR TRANSISTOR
DE2641752A1 (en) METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR
EP0005185A1 (en) Method for simultaneously forming Schottky-barrier diodes and ohmic contacts on doped semiconductor regions
DE69016840T2 (en) Process for the production of a lateral bipolar transistor.
DE2633714C2 (en) Integrated semiconductor circuit arrangement with a bipolar transistor and method for its production
DE2420239A1 (en) METHOD FOR MANUFACTURING DOUBLE DIFFUSED LATERAL TRANSISTORS
DE3587364T2 (en) Field effect transistor with self-aligned gate electrode and method for its production.

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB

17P Request for examination filed
GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 2860161

Country of ref document: DE

Date of ref document: 19801218

KL Correction list

Free format text: 81/01

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19840619

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19890531

Year of fee payment: 12

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19890602

GBPC Gb: european patent ceased through non-payment of renewal fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19900301

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19910228

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT