DE69914294T2 - Verfahren zur Herstellung einer leitenden Struktur - Google Patents
Verfahren zur Herstellung einer leitenden Struktur Download PDFInfo
- Publication number
- DE69914294T2 DE69914294T2 DE1999614294 DE69914294T DE69914294T2 DE 69914294 T2 DE69914294 T2 DE 69914294T2 DE 1999614294 DE1999614294 DE 1999614294 DE 69914294 T DE69914294 T DE 69914294T DE 69914294 T2 DE69914294 T2 DE 69914294T2
- Authority
- DE
- Germany
- Prior art keywords
- film
- substrate
- germ
- copper
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
- H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US19892298A | 1998-11-24 | 1998-11-24 | |
| US198922 | 1998-11-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69914294D1 DE69914294D1 (de) | 2004-02-26 |
| DE69914294T2 true DE69914294T2 (de) | 2004-11-18 |
Family
ID=22735460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE1999614294 Expired - Fee Related DE69914294T2 (de) | 1998-11-24 | 1999-11-10 | Verfahren zur Herstellung einer leitenden Struktur |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1005078B1 (https=) |
| JP (1) | JP4444420B2 (https=) |
| KR (1) | KR100647996B1 (https=) |
| CN (1) | CN1255746A (https=) |
| DE (1) | DE69914294T2 (https=) |
| TW (1) | TW436990B (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6423200B1 (en) * | 1999-09-30 | 2002-07-23 | Lam Research Corporation | Copper interconnect seed layer treatment methods and apparatuses for treating the same |
| EP1111096A3 (en) * | 1999-12-15 | 2004-02-11 | Shipley Company LLC | Seed layer repair method |
| KR100400765B1 (ko) | 2000-11-13 | 2003-10-08 | 엘지.필립스 엘시디 주식회사 | 박막 형성방법 및 이를 적용한 액정표시소자의 제조방법 |
| US6849173B1 (en) * | 2002-06-12 | 2005-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Technique to enhance the yield of copper interconnections |
| KR20040001470A (ko) * | 2002-06-28 | 2004-01-07 | 주식회사 하이닉스반도체 | 반도체 소자의 배선 형성을 위한 구리 씨앗층 형성 방법 |
| KR100808601B1 (ko) | 2006-12-28 | 2008-02-29 | 주식회사 하이닉스반도체 | 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법 |
| CN104299958B (zh) * | 2013-07-16 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及互连结构的形成方法 |
| CN111031683B (zh) * | 2019-12-23 | 2021-10-08 | 沪士电子股份有限公司 | 一种pcb生产工艺中图形电镀陪镀板的设计和使用方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0783168B2 (ja) * | 1988-04-13 | 1995-09-06 | 株式会社日立製作所 | プリント板の製造方法 |
| US5391517A (en) * | 1993-09-13 | 1995-02-21 | Motorola Inc. | Process for forming copper interconnect structure |
| WO1998027585A1 (en) * | 1996-12-16 | 1998-06-25 | International Business Machines Corporation | Electroplated interconnection structures on integrated circuit chips |
-
1999
- 1999-11-01 TW TW088118965A patent/TW436990B/zh not_active IP Right Cessation
- 1999-11-10 EP EP99122376A patent/EP1005078B1/en not_active Expired - Lifetime
- 1999-11-10 DE DE1999614294 patent/DE69914294T2/de not_active Expired - Fee Related
- 1999-11-18 JP JP32766499A patent/JP4444420B2/ja not_active Expired - Fee Related
- 1999-11-23 KR KR1019990052119A patent/KR100647996B1/ko not_active Expired - Fee Related
- 1999-11-23 CN CN99124491A patent/CN1255746A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000035623A (ko) | 2000-06-26 |
| EP1005078B1 (en) | 2004-01-21 |
| CN1255746A (zh) | 2000-06-07 |
| TW436990B (en) | 2001-05-28 |
| JP4444420B2 (ja) | 2010-03-31 |
| EP1005078A1 (en) | 2000-05-31 |
| KR100647996B1 (ko) | 2006-11-23 |
| DE69914294D1 (de) | 2004-02-26 |
| JP2000164718A (ja) | 2000-06-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US |
|
| 8339 | Ceased/non-payment of the annual fee |