TW436990B - Process for forming a semiconductor device - Google Patents

Process for forming a semiconductor device Download PDF

Info

Publication number
TW436990B
TW436990B TW088118965A TW88118965A TW436990B TW 436990 B TW436990 B TW 436990B TW 088118965 A TW088118965 A TW 088118965A TW 88118965 A TW88118965 A TW 88118965A TW 436990 B TW436990 B TW 436990B
Authority
TW
Taiwan
Prior art keywords
seed film
film
substrate
forming
semiconductor device
Prior art date
Application number
TW088118965A
Other languages
English (en)
Chinese (zh)
Inventor
Robert D Mikkola
Rina Chowdury
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW436990B publication Critical patent/TW436990B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
TW088118965A 1998-11-24 1999-11-01 Process for forming a semiconductor device TW436990B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US19892298A 1998-11-24 1998-11-24

Publications (1)

Publication Number Publication Date
TW436990B true TW436990B (en) 2001-05-28

Family

ID=22735460

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088118965A TW436990B (en) 1998-11-24 1999-11-01 Process for forming a semiconductor device

Country Status (6)

Country Link
EP (1) EP1005078B1 (https=)
JP (1) JP4444420B2 (https=)
KR (1) KR100647996B1 (https=)
CN (1) CN1255746A (https=)
DE (1) DE69914294T2 (https=)
TW (1) TW436990B (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423200B1 (en) * 1999-09-30 2002-07-23 Lam Research Corporation Copper interconnect seed layer treatment methods and apparatuses for treating the same
EP1111096A3 (en) * 1999-12-15 2004-02-11 Shipley Company LLC Seed layer repair method
KR100400765B1 (ko) 2000-11-13 2003-10-08 엘지.필립스 엘시디 주식회사 박막 형성방법 및 이를 적용한 액정표시소자의 제조방법
US6849173B1 (en) * 2002-06-12 2005-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Technique to enhance the yield of copper interconnections
KR20040001470A (ko) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 반도체 소자의 배선 형성을 위한 구리 씨앗층 형성 방법
KR100808601B1 (ko) 2006-12-28 2008-02-29 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
CN104299958B (zh) * 2013-07-16 2018-11-16 中芯国际集成电路制造(上海)有限公司 互连结构及互连结构的形成方法
CN111031683B (zh) * 2019-12-23 2021-10-08 沪士电子股份有限公司 一种pcb生产工艺中图形电镀陪镀板的设计和使用方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783168B2 (ja) * 1988-04-13 1995-09-06 株式会社日立製作所 プリント板の製造方法
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
WO1998027585A1 (en) * 1996-12-16 1998-06-25 International Business Machines Corporation Electroplated interconnection structures on integrated circuit chips

Also Published As

Publication number Publication date
KR20000035623A (ko) 2000-06-26
EP1005078B1 (en) 2004-01-21
CN1255746A (zh) 2000-06-07
JP4444420B2 (ja) 2010-03-31
EP1005078A1 (en) 2000-05-31
KR100647996B1 (ko) 2006-11-23
DE69914294D1 (de) 2004-02-26
JP2000164718A (ja) 2000-06-16
DE69914294T2 (de) 2004-11-18

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees