JP4444420B2 - 導電性構造および半導体装置を形成するためのプロセス - Google Patents

導電性構造および半導体装置を形成するためのプロセス Download PDF

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Publication number
JP4444420B2
JP4444420B2 JP32766499A JP32766499A JP4444420B2 JP 4444420 B2 JP4444420 B2 JP 4444420B2 JP 32766499 A JP32766499 A JP 32766499A JP 32766499 A JP32766499 A JP 32766499A JP 4444420 B2 JP4444420 B2 JP 4444420B2
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JP
Japan
Prior art keywords
seed film
copper
substrate
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32766499A
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English (en)
Japanese (ja)
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JP2000164718A5 (https=
JP2000164718A (ja
Inventor
ロバート・ディー・ミッコラ
リナ・チョウハリー
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NXP USA Inc
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NXP USA Inc
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Publication date
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Publication of JP2000164718A publication Critical patent/JP2000164718A/ja
Publication of JP2000164718A5 publication Critical patent/JP2000164718A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
JP32766499A 1998-11-24 1999-11-18 導電性構造および半導体装置を形成するためのプロセス Expired - Fee Related JP4444420B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19892298A 1998-11-24 1998-11-24
US198922 1998-11-24

Publications (3)

Publication Number Publication Date
JP2000164718A JP2000164718A (ja) 2000-06-16
JP2000164718A5 JP2000164718A5 (https=) 2007-01-11
JP4444420B2 true JP4444420B2 (ja) 2010-03-31

Family

ID=22735460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32766499A Expired - Fee Related JP4444420B2 (ja) 1998-11-24 1999-11-18 導電性構造および半導体装置を形成するためのプロセス

Country Status (6)

Country Link
EP (1) EP1005078B1 (https=)
JP (1) JP4444420B2 (https=)
KR (1) KR100647996B1 (https=)
CN (1) CN1255746A (https=)
DE (1) DE69914294T2 (https=)
TW (1) TW436990B (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423200B1 (en) * 1999-09-30 2002-07-23 Lam Research Corporation Copper interconnect seed layer treatment methods and apparatuses for treating the same
EP1111096A3 (en) * 1999-12-15 2004-02-11 Shipley Company LLC Seed layer repair method
KR100400765B1 (ko) 2000-11-13 2003-10-08 엘지.필립스 엘시디 주식회사 박막 형성방법 및 이를 적용한 액정표시소자의 제조방법
US6849173B1 (en) * 2002-06-12 2005-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Technique to enhance the yield of copper interconnections
KR20040001470A (ko) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 반도체 소자의 배선 형성을 위한 구리 씨앗층 형성 방법
KR100808601B1 (ko) 2006-12-28 2008-02-29 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
CN104299958B (zh) * 2013-07-16 2018-11-16 中芯国际集成电路制造(上海)有限公司 互连结构及互连结构的形成方法
CN111031683B (zh) * 2019-12-23 2021-10-08 沪士电子股份有限公司 一种pcb生产工艺中图形电镀陪镀板的设计和使用方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783168B2 (ja) * 1988-04-13 1995-09-06 株式会社日立製作所 プリント板の製造方法
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
WO1998027585A1 (en) * 1996-12-16 1998-06-25 International Business Machines Corporation Electroplated interconnection structures on integrated circuit chips

Also Published As

Publication number Publication date
KR20000035623A (ko) 2000-06-26
EP1005078B1 (en) 2004-01-21
CN1255746A (zh) 2000-06-07
TW436990B (en) 2001-05-28
EP1005078A1 (en) 2000-05-31
KR100647996B1 (ko) 2006-11-23
DE69914294D1 (de) 2004-02-26
JP2000164718A (ja) 2000-06-16
DE69914294T2 (de) 2004-11-18

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