DE69841724D1 - Herstellung von steuer- und freischwebegates von halbleiterfestwertspeichern - Google Patents

Herstellung von steuer- und freischwebegates von halbleiterfestwertspeichern

Info

Publication number
DE69841724D1
DE69841724D1 DE69841724T DE69841724T DE69841724D1 DE 69841724 D1 DE69841724 D1 DE 69841724D1 DE 69841724 T DE69841724 T DE 69841724T DE 69841724 T DE69841724 T DE 69841724T DE 69841724 D1 DE69841724 D1 DE 69841724D1
Authority
DE
Germany
Prior art keywords
freeshold
manufacture
control
reservoir stores
semiconductor reservoir
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69841724T
Other languages
English (en)
Inventor
Steven Keetai Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion LLC filed Critical Spansion LLC
Application granted granted Critical
Publication of DE69841724D1 publication Critical patent/DE69841724D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69841724T 1997-12-18 1998-12-18 Herstellung von steuer- und freischwebegates von halbleiterfestwertspeichern Expired - Lifetime DE69841724D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/992,960 US6258669B1 (en) 1997-12-18 1997-12-18 Methods and arrangements for improved formation of control and floating gates in non-volatile memory semiconductor devices
PCT/US1998/026848 WO1999031730A1 (en) 1997-12-18 1998-12-18 Formation of control and floating gates of semiconductor non-volatile memories

Publications (1)

Publication Number Publication Date
DE69841724D1 true DE69841724D1 (de) 2010-07-29

Family

ID=25538937

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69841724T Expired - Lifetime DE69841724D1 (de) 1997-12-18 1998-12-18 Herstellung von steuer- und freischwebegates von halbleiterfestwertspeichern

Country Status (6)

Country Link
US (1) US6258669B1 (de)
EP (1) EP1042810B1 (de)
JP (1) JP4606580B2 (de)
KR (1) KR100554707B1 (de)
DE (1) DE69841724D1 (de)
WO (1) WO1999031730A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6682978B1 (en) 1999-08-30 2004-01-27 Advanced Micro Devices, Inc. Integrated circuit having increased gate coupling capacitance
US6576949B1 (en) 1999-08-30 2003-06-10 Advanced Micro Devices, Inc. Integrated circuit having optimized gate coupling capacitance
KR100356468B1 (ko) * 1999-12-29 2002-10-18 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
US6232635B1 (en) * 2000-04-06 2001-05-15 Advanced Micro Devices, Inc. Method to fabricate a high coupling flash cell with less silicide seam problem
IT1318145B1 (it) * 2000-07-11 2003-07-23 St Microelectronics Srl Processo per fabbricare una cella di memoria non-volatile con unaregione di gate flottante autoallineata all'isolamento e con un alto
JP4051175B2 (ja) * 2000-11-17 2008-02-20 スパンション エルエルシー 不揮発性半導体メモリ装置および製造方法
JP4439142B2 (ja) 2001-06-26 2010-03-24 株式会社東芝 不揮発性半導体メモリの製造方法
US6645796B2 (en) * 2001-11-21 2003-11-11 International Business Machines Corporation Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices
US6911370B2 (en) * 2002-05-24 2005-06-28 Hynix Semiconductor, Inc. Flash memory device having poly spacers
GB0405325D0 (en) * 2004-03-10 2004-04-21 Koninkl Philips Electronics Nv Trench-gate transistors and their manufacture
US8642441B1 (en) 2006-12-15 2014-02-04 Spansion Llc Self-aligned STI with single poly for manufacturing a flash memory device
US8551858B2 (en) * 2010-02-03 2013-10-08 Spansion Llc Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory
KR101858521B1 (ko) * 2011-06-13 2018-06-28 삼성전자주식회사 비휘발성 메모리 장치의 제조 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810726B2 (ja) * 1984-07-06 1996-01-31 株式会社東芝 半導体装置の製造方法
JPH0715954B2 (ja) * 1985-11-30 1995-02-22 株式会社東芝 不揮発性半導体記憶装置の製造方法
US4980309A (en) * 1987-11-30 1990-12-25 Texas Instruments, Incorporated Method of making high density EEPROM
JPH0210875A (ja) * 1988-06-29 1990-01-16 Mitsubishi Electric Corp 半導体装置の製造方法
JPH03246974A (ja) 1990-02-26 1991-11-05 Toshiba Corp 半導体記憶装置の製造方法
US5021848A (en) * 1990-03-13 1991-06-04 Chiu Te Long Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5266509A (en) * 1990-05-11 1993-11-30 North American Philips Corporation Fabrication method for a floating-gate field-effect transistor structure
JPH04323877A (ja) 1991-04-24 1992-11-13 Nec Kyushu Ltd 半導体記憶装置
EP0511628A3 (en) 1991-04-30 1993-09-22 Texas Instruments Incorporated Insulator for integrated circuits formed by high-pressure oxidation
JP3548984B2 (ja) * 1991-11-14 2004-08-04 富士通株式会社 半導体装置の製造方法
JP2774734B2 (ja) * 1992-05-26 1998-07-09 株式会社東芝 半導体記憶装置およびその製造方法
JPH0897306A (ja) 1994-09-29 1996-04-12 Toshiba Corp 半導体装置及びその製造方法
JP3162264B2 (ja) * 1995-05-30 2001-04-25 シャープ株式会社 フラッシュメモリの書換え方法
US5702964A (en) * 1995-10-17 1997-12-30 Lg Semicon, Co., Ltd. Method for forming a semiconductor device having a floating gate
JP2734433B2 (ja) * 1995-10-31 1998-03-30 日本電気株式会社 不揮発性半導体記憶装置の製造方法
US5686332A (en) * 1995-11-13 1997-11-11 United Microelectronics Corporation Process for fabricating flash memory devices
JPH10261775A (ja) 1996-10-29 1998-09-29 Texas Instr Inc <Ti> Ｅｐｒｏｍの２つのセル間に電気的隔離を備える方法

Also Published As

Publication number Publication date
WO1999031730A1 (en) 1999-06-24
US6258669B1 (en) 2001-07-10
JP4606580B2 (ja) 2011-01-05
EP1042810A1 (de) 2000-10-11
EP1042810B1 (de) 2010-06-16
JP2002509359A (ja) 2002-03-26
KR20010033346A (ko) 2001-04-25
KR100554707B1 (ko) 2006-02-24

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