DE69832162D1 - Herstellungsverfahren für ein elektronisches Bauelement, das MOS Transistoren mit salizidierten Übergängen und nicht salizidierten Widerständen enthält - Google Patents

Herstellungsverfahren für ein elektronisches Bauelement, das MOS Transistoren mit salizidierten Übergängen und nicht salizidierten Widerständen enthält

Info

Publication number
DE69832162D1
DE69832162D1 DE69832162T DE69832162T DE69832162D1 DE 69832162 D1 DE69832162 D1 DE 69832162D1 DE 69832162 T DE69832162 T DE 69832162T DE 69832162 T DE69832162 T DE 69832162T DE 69832162 D1 DE69832162 D1 DE 69832162D1
Authority
DE
Germany
Prior art keywords
salicided
resistors
electronic device
device including
mos transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69832162T
Other languages
English (en)
Inventor
Matteo Patelmo
Nadia Galbiati
Libera Giovanna Dalla
Bruno Vajana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69832162D1 publication Critical patent/DE69832162D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
DE69832162T 1998-07-22 1998-07-22 Herstellungsverfahren für ein elektronisches Bauelement, das MOS Transistoren mit salizidierten Übergängen und nicht salizidierten Widerständen enthält Expired - Lifetime DE69832162D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98830444A EP0975021B1 (de) 1998-07-22 1998-07-22 Herstellungsverfahren für ein elektronisches Bauelement, das MOS Transistoren mit salizidierten Übergängen und nicht salizidierten Widerständen enthält

Publications (1)

Publication Number Publication Date
DE69832162D1 true DE69832162D1 (de) 2005-12-08

Family

ID=8236723

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69832162T Expired - Lifetime DE69832162D1 (de) 1998-07-22 1998-07-22 Herstellungsverfahren für ein elektronisches Bauelement, das MOS Transistoren mit salizidierten Übergängen und nicht salizidierten Widerständen enthält

Country Status (3)

Country Link
US (1) US6300181B1 (de)
EP (1) EP0975021B1 (de)
DE (1) DE69832162D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1403909A1 (de) * 2002-09-30 2004-03-31 STMicroelectronics S.r.l. Verfahren zur Herstellung integrierter Widerstandselemente mit Silizidationsschutz
JP2005191228A (ja) * 2003-12-25 2005-07-14 Sanyo Electric Co Ltd 半導体装置の製造方法
US9786777B2 (en) 2013-08-30 2017-10-10 Hewlett-Packard Development Company, L.P. Semiconductor device and method of making same
WO2015137960A1 (en) 2014-03-14 2015-09-17 Hewlett-Packard Development Company, L.P. Eprom cell with modified floating gate

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4339869A (en) 1980-09-15 1982-07-20 General Electric Company Method of making low resistance contacts in semiconductor devices by ion induced silicides
US4830976A (en) * 1984-10-01 1989-05-16 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit resistor
JPS63204638A (ja) * 1987-02-19 1988-08-24 Nec Corp Ｍｏｓ型半導体集積回路装置
US4906589A (en) * 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
US5001082A (en) * 1989-04-12 1991-03-19 Mcnc Self-aligned salicide process for forming semiconductor devices and devices formed thereby
US5134088A (en) * 1990-04-27 1992-07-28 Digital Equipment Corporation Precision resistor in self-aligned silicided mos process
US5474941A (en) 1990-12-28 1995-12-12 Sharp Kabushiki Kaisha Method for producing an active matrix substrate
EP0493113B1 (de) 1990-12-28 1997-03-19 Sharp Kabushiki Kaisha Ein Verfahren zum Herstellen eines Dünnfilm-Transistors und eines Aktive-Matrix-Substrates für Flüssig-Kristall-Anzeige-Anordnungen
JPH05283427A (ja) 1991-02-18 1993-10-29 Hitachi Ltd 薄膜トランジスタの製造方法及びそれを用いたアクテブマトリックス型液晶表示装置
EP0545363A1 (de) * 1991-12-06 1993-06-09 National Semiconductor Corporation Herstellungsverfahren für eine integrierte Schaltung und Struktur
US5346833A (en) * 1993-04-05 1994-09-13 Industrial Technology Research Institute Simplified method of making active matrix liquid crystal display
JPH07106570A (ja) * 1993-10-05 1995-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
JPH07211915A (ja) 1994-01-20 1995-08-11 Casio Comput Co Ltd 薄膜トランジスタの製造方法
US5496750A (en) * 1994-09-19 1996-03-05 Texas Instruments Incorporated Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition
JP3297784B2 (ja) * 1994-09-29 2002-07-02 ソニー株式会社 拡散層抵抗の形成方法
US5705405A (en) * 1994-09-30 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of making the film transistor with all-around gate electrode
US5670812A (en) * 1995-09-29 1997-09-23 International Business Machines Corporation Field effect transistor having contact layer of transistor gate electrode material
US5717223A (en) * 1995-12-22 1998-02-10 Xerox Corporation Array with amorphous silicon TFTs in which channel leads overlap insulating region no more than maximum overlap
US5780349A (en) * 1997-02-20 1998-07-14 National Semiconductor Corporation Self-aligned MOSFET gate/source/drain salicide formation
US5994228A (en) * 1997-04-11 1999-11-30 Vanguard International Semiconductor Corporation Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes
US6069398A (en) * 1997-08-01 2000-05-30 Advanced Micro Devices, Inc. Thin film resistor and fabrication method thereof
TW386255B (en) * 1998-05-18 2000-04-01 United Microelectronics Corp Method for self-aligned silicide process

Also Published As

Publication number Publication date
EP0975021A1 (de) 2000-01-26
US6300181B1 (en) 2001-10-09
EP0975021B1 (de) 2005-11-02

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