DE69739768D1 - Methode zur verringerung von plasmainduzierten aufladungsschäden - Google Patents

Methode zur verringerung von plasmainduzierten aufladungsschäden

Info

Publication number
DE69739768D1
DE69739768D1 DE69739768T DE69739768T DE69739768D1 DE 69739768 D1 DE69739768 D1 DE 69739768D1 DE 69739768 T DE69739768 T DE 69739768T DE 69739768 T DE69739768 T DE 69739768T DE 69739768 D1 DE69739768 D1 DE 69739768D1
Authority
DE
Germany
Prior art keywords
conductive layer
selected portion
power setting
induced charge
reducing plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69739768T
Other languages
German (de)
English (en)
Inventor
Roger Patrick
Stanley C Siu
Luisarita Atzei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Application granted granted Critical
Publication of DE69739768D1 publication Critical patent/DE69739768D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas

Landscapes

  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Secondary Cells (AREA)
DE69739768T 1996-12-18 1997-12-18 Methode zur verringerung von plasmainduzierten aufladungsschäden Expired - Lifetime DE69739768D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/768,618 US6309979B1 (en) 1996-12-18 1996-12-18 Methods for reducing plasma-induced charging damage
PCT/US1997/024227 WO1998027581A1 (en) 1996-12-18 1997-12-18 Methods for reducing plasma-induced charging damage

Publications (1)

Publication Number Publication Date
DE69739768D1 true DE69739768D1 (de) 2010-04-01

Family

ID=25083007

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69739768T Expired - Lifetime DE69739768D1 (de) 1996-12-18 1997-12-18 Methode zur verringerung von plasmainduzierten aufladungsschäden

Country Status (8)

Country Link
US (1) US6309979B1 (enExample)
EP (1) EP0954877B1 (enExample)
JP (1) JP2001506421A (enExample)
KR (1) KR100535961B1 (enExample)
AT (1) ATE458272T1 (enExample)
DE (1) DE69739768D1 (enExample)
TW (1) TW380285B (enExample)
WO (1) WO1998027581A1 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6309979B1 (en) * 1996-12-18 2001-10-30 Lam Research Corporation Methods for reducing plasma-induced charging damage
TW451344B (en) * 2000-03-15 2001-08-21 Winbond Electronics Corp Profile controlling method to etch metal layer
DE10050047B4 (de) * 2000-10-10 2006-07-13 Promos Technologies, Inc. Trockenreinigungsverfahren statt der herkömmlichen Nassreinigung nach der Ätzung von Metallen
DE10111989C2 (de) * 2001-03-13 2003-11-06 Infineon Technologies Ag Verfahren zur Herstellung von Strukturen in einer Halbleiterschaltung, wobei eine Verringerung plasmainduzierter Aufladung eintritt
US6686254B2 (en) * 2001-04-27 2004-02-03 Motorola, Inc. Semiconductor structure and method for reducing charge damage
US7109122B2 (en) * 2002-11-29 2006-09-19 Tokyo Electron Limited Method and apparatus for reducing substrate charging damage
US7098141B1 (en) 2003-03-03 2006-08-29 Lam Research Corporation Use of silicon containing gas for CD and profile feature enhancements of gate and shallow trench structures
US6869542B2 (en) * 2003-03-12 2005-03-22 International Business Machines Corporation Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials
KR20050033216A (ko) * 2003-10-06 2005-04-12 동부아남반도체 주식회사 고밀도 플라즈마 설비
US7164095B2 (en) * 2004-07-07 2007-01-16 Noritsu Koki Co., Ltd. Microwave plasma nozzle with enhanced plume stability and heating efficiency
US7806077B2 (en) 2004-07-30 2010-10-05 Amarante Technologies, Inc. Plasma nozzle array for providing uniform scalable microwave plasma generation
US20060021980A1 (en) * 2004-07-30 2006-02-02 Lee Sang H System and method for controlling a power distribution within a microwave cavity
US7271363B2 (en) * 2004-09-01 2007-09-18 Noritsu Koki Co., Ltd. Portable microwave plasma systems including a supply line for gas and microwaves
US7189939B2 (en) * 2004-09-01 2007-03-13 Noritsu Koki Co., Ltd. Portable microwave plasma discharge unit
US20060052883A1 (en) * 2004-09-08 2006-03-09 Lee Sang H System and method for optimizing data acquisition of plasma using a feedback control module
KR100584781B1 (ko) * 2004-12-02 2006-05-29 삼성전자주식회사 반도체 장치의 제조 방법 및 이를 이용한 박막 제조 방법
CN100413034C (zh) * 2005-12-08 2008-08-20 北京北方微电子基地设备工艺研究中心有限责任公司 一种能够防止器件等离子体损伤的多晶硅刻蚀工艺
JP4678688B2 (ja) * 2006-02-27 2011-04-27 次世代半導体材料技術研究組合 プラズマ処理終了方法
US7846800B2 (en) * 2008-03-06 2010-12-07 Chartered Semiconductor Manufacturing, Ltd. Avoiding plasma charging in integrated circuits
US20100326954A1 (en) * 2009-06-26 2010-12-30 Zhen Yu Zhuo Method of etching a multi-layer
WO2011162770A1 (en) 2010-06-25 2011-12-29 Tousimis Anastasios J Integrated processing and critical point drying systems for semiconductor and mems devices
JP6504755B2 (ja) * 2014-06-25 2019-04-24 キヤノン株式会社 半導体装置の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102318A (ja) * 1986-10-20 1988-05-07 Tokyo Electron Ltd プラズマエツチング方法
US4808259A (en) * 1988-01-25 1989-02-28 Intel Corporation Plasma etching process for MOS circuit pregate etching utiliizing a multi-step power reduction recipe
US5160407A (en) 1991-01-02 1992-11-03 Applied Materials, Inc. Low pressure anisotropic etch process for tantalum silicide or titanium silicide layer formed over polysilicon layer deposited on silicon oxide layer on semiconductor wafer
DE4132564C2 (de) 1991-09-30 1994-11-03 Siemens Ag Verfahren zum Plasmaätzen mit mikrowellenenergiegespeister Voranregung der Ätzgase bei der Herstellung integrierter Halbleiterschaltungen und Verwendung des Verfahrens
US5242532A (en) 1992-03-20 1993-09-07 Vlsi Technology, Inc. Dual mode plasma etching system and method of plasma endpoint detection
JP3211391B2 (ja) 1992-07-29 2001-09-25 松下電器産業株式会社 ドライエッチング方法
JP3360404B2 (ja) 1994-04-01 2002-12-24 ソニー株式会社 プラズマエッチング方法
US5582679A (en) 1994-09-12 1996-12-10 Chartered Semiconductor Manufacturing Pte Ltd. Enhanced metal etch process
EP0731501A1 (en) 1995-03-08 1996-09-11 International Business Machines Corporation Method for plasma etching an oxide/polycide structure
US5667630A (en) 1995-04-28 1997-09-16 Vanguard International Semiconductor Corporation Low charge-up reactive ion metal etch process
US6309979B1 (en) * 1996-12-18 2001-10-30 Lam Research Corporation Methods for reducing plasma-induced charging damage

Also Published As

Publication number Publication date
KR100535961B1 (ko) 2005-12-09
EP0954877B1 (en) 2010-02-17
WO1998027581A1 (en) 1998-06-25
US6309979B1 (en) 2001-10-30
KR20000057465A (ko) 2000-09-15
TW380285B (en) 2000-01-21
JP2001506421A (ja) 2001-05-15
EP0954877A1 (en) 1999-11-10
ATE458272T1 (de) 2010-03-15

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