DE69733388D1 - Halbleiteranordnung mit einer Schaltung zur Verhinderung von Latch-up - Google Patents

Halbleiteranordnung mit einer Schaltung zur Verhinderung von Latch-up

Info

Publication number
DE69733388D1
DE69733388D1 DE69733388T DE69733388T DE69733388D1 DE 69733388 D1 DE69733388 D1 DE 69733388D1 DE 69733388 T DE69733388 T DE 69733388T DE 69733388 T DE69733388 T DE 69733388T DE 69733388 D1 DE69733388 D1 DE 69733388D1
Authority
DE
Germany
Prior art keywords
circuit
semiconductor arrangement
preventing latch
latch
preventing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69733388T
Other languages
English (en)
Other versions
DE69733388T2 (de
Inventor
Katsuhiro Kato
Hidekazu Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69733388D1 publication Critical patent/DE69733388D1/de
Publication of DE69733388T2 publication Critical patent/DE69733388T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE69733388T 1996-08-21 1997-08-20 Halbleiteranordnung mit einer Schaltung zur Verhinderung von Latch-up Expired - Lifetime DE69733388T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8220079A JPH1065020A (ja) 1996-08-21 1996-08-21 半導体装置
JP22007996 1996-08-21

Publications (2)

Publication Number Publication Date
DE69733388D1 true DE69733388D1 (de) 2005-07-07
DE69733388T2 DE69733388T2 (de) 2006-04-27

Family

ID=16745611

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69733388T Expired - Lifetime DE69733388T2 (de) 1996-08-21 1997-08-20 Halbleiteranordnung mit einer Schaltung zur Verhinderung von Latch-up

Country Status (6)

Country Link
US (1) US5962902A (de)
EP (1) EP0827206B1 (de)
JP (1) JPH1065020A (de)
KR (1) KR100336154B1 (de)
DE (1) DE69733388T2 (de)
TW (1) TW334625B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4376348B2 (ja) * 1998-05-18 2009-12-02 パナソニック株式会社 半導体装置
US6137143A (en) * 1998-06-30 2000-10-24 Intel Corporation Diode and transistor design for high speed I/O
JP3348782B2 (ja) 1999-07-22 2002-11-20 日本電気株式会社 半導体装置の製造方法
US6407898B1 (en) * 2000-01-18 2002-06-18 Taiwan Semiconductor Manufacturing Company Ltd. Protection means for preventing power-on sequence induced latch-up
US7304354B2 (en) * 2004-02-17 2007-12-04 Silicon Space Technology Corp. Buried guard ring and radiation hardened isolation structures and fabrication methods
US7773442B2 (en) 2004-06-25 2010-08-10 Cypress Semiconductor Corporation Memory cell array latchup prevention
US9842629B2 (en) 2004-06-25 2017-12-12 Cypress Semiconductor Corporation Memory cell array latchup prevention
JP2006269902A (ja) * 2005-03-25 2006-10-05 Oki Electric Ind Co Ltd 半導体集積回路
JP2007103863A (ja) * 2005-10-07 2007-04-19 Nec Electronics Corp 半導体デバイス
DE602007005289D1 (de) * 2006-01-24 2010-04-29 St Microelectronics Sa Schutzschaltung für eine integrierte Schaltung gegen parasitäre latch-up Phänomene
KR101043737B1 (ko) * 2007-02-15 2011-06-24 주식회사 하이닉스반도체 정전기 방전 보호 소자
US8278684B1 (en) * 2007-12-12 2012-10-02 Cypress Semiconductor Corporation Voltage protection device
EP2290691A1 (de) * 2009-08-24 2011-03-02 STmicroelectronics SA Schutzvorrichtung für einen integrierten Schaltkreis gegen elektrostatische Entladungen
US10038058B2 (en) 2016-05-07 2018-07-31 Silicon Space Technology Corporation FinFET device structure and method for forming same
JP7048160B2 (ja) * 2021-01-13 2022-04-05 ラピスセミコンダクタ株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4476476A (en) * 1979-04-05 1984-10-09 National Semiconductor Corporation CMOS Input and output protection circuit
DE3422132C1 (de) * 1984-06-14 1986-01-09 Texas Instruments Deutschland Gmbh, 8050 Freising Schutzschaltungsanordnung
US4647956A (en) * 1985-02-12 1987-03-03 Cypress Semiconductor Corp. Back biased CMOS device with means for eliminating latchup
US4870530A (en) * 1988-06-27 1989-09-26 Advanced Micro Devices, Inc. Electrostatic discharge protection circuitry for any two external pins of an I.C. package
JPH04247654A (ja) * 1991-02-04 1992-09-03 Nissan Motor Co Ltd 入出力保護回路
JP2599037B2 (ja) * 1991-04-24 1997-04-09 三洋電機株式会社 半導体集積回路
US5468984A (en) * 1994-11-02 1995-11-21 Texas Instruments Incorporated ESD protection structure using LDMOS diodes with thick copper interconnect
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation

Also Published As

Publication number Publication date
EP0827206B1 (de) 2005-06-01
DE69733388T2 (de) 2006-04-27
KR100336154B1 (ko) 2002-06-20
EP0827206A2 (de) 1998-03-04
JPH1065020A (ja) 1998-03-06
TW334625B (en) 1998-06-21
KR19980018812A (ko) 1998-06-05
US5962902A (en) 1999-10-05
EP0827206A3 (de) 1998-04-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: BOCKHORNI & KOLLEGEN, 80687 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP