DE69429467D1 - Halbleiteranordnung mit einer Isolationszone - Google Patents
Halbleiteranordnung mit einer IsolationszoneInfo
- Publication number
- DE69429467D1 DE69429467D1 DE69429467T DE69429467T DE69429467D1 DE 69429467 D1 DE69429467 D1 DE 69429467D1 DE 69429467 T DE69429467 T DE 69429467T DE 69429467 T DE69429467 T DE 69429467T DE 69429467 D1 DE69429467 D1 DE 69429467D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor arrangement
- isolation zone
- isolation
- zone
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5049656A JPH06268054A (ja) | 1993-03-10 | 1993-03-10 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69429467D1 true DE69429467D1 (de) | 2002-01-31 |
DE69429467T2 DE69429467T2 (de) | 2002-08-08 |
Family
ID=12837235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69429467T Expired - Lifetime DE69429467T2 (de) | 1993-03-10 | 1994-03-08 | Halbleiteranordnung mit einer Isolationszone |
Country Status (4)
Country | Link |
---|---|
US (1) | US5449946A (de) |
EP (1) | EP0615286B1 (de) |
JP (1) | JPH06268054A (de) |
DE (1) | DE69429467T2 (de) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5644157A (en) * | 1992-12-25 | 1997-07-01 | Nippondenso Co., Ltd. | High withstand voltage type semiconductor device having an isolation region |
JP3818673B2 (ja) * | 1993-03-10 | 2006-09-06 | 株式会社デンソー | 半導体装置 |
JP2773611B2 (ja) * | 1993-11-17 | 1998-07-09 | 株式会社デンソー | 絶縁物分離半導体装置 |
US6104078A (en) * | 1994-03-09 | 2000-08-15 | Denso Corporation | Design for a semiconductor device having elements isolated by insulating regions |
KR970052022A (ko) * | 1995-12-30 | 1997-07-29 | 김주용 | 에스 오 아이 기판 제조방법 |
TW309647B (de) * | 1995-12-30 | 1997-07-01 | Hyundai Electronics Ind | |
US6242792B1 (en) | 1996-07-02 | 2001-06-05 | Denso Corporation | Semiconductor device having oblique portion as reflection |
JP2998662B2 (ja) * | 1996-11-15 | 2000-01-11 | 日本電気株式会社 | 半導体装置 |
DE19808514A1 (de) * | 1997-02-28 | 1998-09-10 | Int Rectifier Corp | Halbleiterbauteil sowie Verfahren zu seiner Herstellung |
JP3422209B2 (ja) * | 1997-03-17 | 2003-06-30 | 株式会社デンソー | 半導体装置 |
SE522812C2 (sv) * | 1997-03-27 | 2004-03-09 | Ericsson Telefon Ab L M | Anordning och förfarande för att reducera elektriska fältkoncentrationer i elektriska komponenter |
DE19800715A1 (de) * | 1998-01-12 | 1999-07-15 | Bremicker Auto Elektrik | Elektrisches Halbleiterelement sowie Verfahren zur Herstellung eines Halbleiterelementes |
US6150697A (en) * | 1998-04-30 | 2000-11-21 | Denso Corporation | Semiconductor apparatus having high withstand voltage |
JP4617527B2 (ja) | 1999-04-08 | 2011-01-26 | 株式会社デンソー | 回路装置 |
EP1073112A1 (de) | 1999-07-26 | 2001-01-31 | STMicroelectronics S.r.l. | Verfahren zur Herstellung eines SOI-Wafers mittels Oxidierung von vergrabenen Hohlräumen |
US6524890B2 (en) | 1999-11-17 | 2003-02-25 | Denso Corporation | Method for manufacturing semiconductor device having element isolation structure |
US6787872B2 (en) * | 2001-06-26 | 2004-09-07 | International Rectifier Corporation | Lateral conduction superjunction semiconductor device |
JP2003017704A (ja) | 2001-06-29 | 2003-01-17 | Denso Corp | 半導体装置 |
US6791156B2 (en) * | 2001-10-26 | 2004-09-14 | Denso Corporation | Semiconductor device and method for manufacturing it |
KR100854077B1 (ko) * | 2002-05-28 | 2008-08-25 | 페어차일드코리아반도체 주식회사 | 웨이퍼 본딩을 이용한 soi 기판 제조 방법과 이 soi기판을 사용한 상보형 고전압 바이폴라 트랜지스터 제조방법 |
JP4512497B2 (ja) * | 2005-01-31 | 2010-07-28 | イビデン株式会社 | コンデンサ内蔵パッケージ基板及びその製法 |
DE102006013203B3 (de) | 2006-03-22 | 2008-01-10 | Infineon Technologies Ag | Integrierte Halbleiteranordnung mit Rückstromkomplex zur Verringerung eines Substratstroms und Verfahren zu deren Herstellung |
JP5302522B2 (ja) * | 2007-07-02 | 2013-10-02 | スパンション エルエルシー | 半導体装置及びその製造方法 |
US7816759B2 (en) * | 2008-01-09 | 2010-10-19 | Infineon Technologies Ag | Integrated circuit including isolation regions substantially through substrate |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3990102A (en) * | 1974-06-28 | 1976-11-02 | Hitachi, Ltd. | Semiconductor integrated circuits and method of manufacturing the same |
US4231056A (en) * | 1978-10-20 | 1980-10-28 | Harris Corporation | Moat resistor ram cell |
US4470062A (en) * | 1979-08-31 | 1984-09-04 | Hitachi, Ltd. | Semiconductor device having isolation regions |
JPS6060753A (ja) * | 1983-09-14 | 1985-04-08 | Matsushita Electronics Corp | 半導体装置 |
US4661202A (en) * | 1984-02-14 | 1987-04-28 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JPH0654796B2 (ja) * | 1986-07-14 | 1994-07-20 | 株式会社日立製作所 | 複合半導体装置 |
JPS6365641A (ja) * | 1986-09-05 | 1988-03-24 | Nec Corp | 半導体集積回路 |
US5241210A (en) * | 1987-02-26 | 1993-08-31 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
EP0398468A3 (de) * | 1989-05-16 | 1991-03-13 | Kabushiki Kaisha Toshiba | Dielektrisch isoliertes Substrat und Halbleiteranordnung mit diesem Substrat |
JP2979554B2 (ja) * | 1989-09-26 | 1999-11-15 | 株式会社デンソー | 半導体装置の製造方法 |
JPH03148852A (ja) * | 1989-11-06 | 1991-06-25 | Fujitsu Ltd | 半導体装置 |
JP3351803B2 (ja) * | 1991-01-11 | 2002-12-03 | 富士通株式会社 | 半導体集積回路装置の製造方法 |
-
1993
- 1993-03-10 JP JP5049656A patent/JPH06268054A/ja active Pending
-
1994
- 1994-03-08 DE DE69429467T patent/DE69429467T2/de not_active Expired - Lifetime
- 1994-03-08 EP EP94103531A patent/EP0615286B1/de not_active Expired - Lifetime
- 1994-03-09 US US08/208,119 patent/US5449946A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0615286A3 (de) | 1997-09-24 |
DE69429467T2 (de) | 2002-08-08 |
JPH06268054A (ja) | 1994-09-22 |
EP0615286A2 (de) | 1994-09-14 |
EP0615286B1 (de) | 2001-12-19 |
US5449946A (en) | 1995-09-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |