DE69318880D1 - Planarisierungsverfahren von einer integrierten Schaltung - Google Patents

Planarisierungsverfahren von einer integrierten Schaltung

Info

Publication number
DE69318880D1
DE69318880D1 DE69318880T DE69318880T DE69318880D1 DE 69318880 D1 DE69318880 D1 DE 69318880D1 DE 69318880 T DE69318880 T DE 69318880T DE 69318880 T DE69318880 T DE 69318880T DE 69318880 D1 DE69318880 D1 DE 69318880D1
Authority
DE
Germany
Prior art keywords
integrated circuit
planarization process
planarization
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69318880T
Other languages
English (en)
Other versions
DE69318880T2 (de
Inventor
Yih-Shung Lin
Kuei-Wu Huang
Lun-Tseng Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69318880D1 publication Critical patent/DE69318880D1/de
Application granted granted Critical
Publication of DE69318880T2 publication Critical patent/DE69318880T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
DE69318880T 1992-03-31 1993-03-22 Planarisierungsverfahren von einer integrierten Schaltung Expired - Fee Related DE69318880T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86107692A 1992-03-31 1992-03-31

Publications (2)

Publication Number Publication Date
DE69318880D1 true DE69318880D1 (de) 1998-07-09
DE69318880T2 DE69318880T2 (de) 1998-10-08

Family

ID=25334809

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69318880T Expired - Fee Related DE69318880T2 (de) 1992-03-31 1993-03-22 Planarisierungsverfahren von einer integrierten Schaltung

Country Status (4)

Country Link
US (1) US5485035A (de)
EP (1) EP0564136B1 (de)
JP (1) JPH0645330A (de)
DE (1) DE69318880T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710460A (en) * 1995-04-21 1998-01-20 International Business Machines Corporation Structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric
US5675185A (en) * 1995-09-29 1997-10-07 International Business Machines Corporation Semiconductor structure incorporating thin film transistors with undoped cap oxide layers
KR100219562B1 (ko) * 1996-10-28 1999-09-01 윤종용 반도체장치의 다층 배선 형성방법
US6849557B1 (en) * 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
EP0954017A3 (de) * 1998-04-16 2000-08-09 STMicroelectronics, Inc. Eine Halbleiterstruktur mit einem verbesserten Pre-metal-Dielektrik-Stapel
US6277758B1 (en) 1998-07-23 2001-08-21 Micron Technology, Inc. Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher
GB2340302B (en) * 1998-07-29 2000-07-26 United Microelectronics Corp Method of manufacture using dual damascene process
US6207989B1 (en) * 1999-03-16 2001-03-27 Vantis Corporation Non-volatile memory device having a high-reliability composite insulation layer
US6127260A (en) * 1999-07-16 2000-10-03 Taiwan Semiconductor Manufacturing Company Method of forming a tee shaped tungsten plug structure to avoid high aspect ratio contact holes in embedded DRAM devices
US6339027B1 (en) * 1999-11-22 2002-01-15 Chartered Semiconductor Manufacturing Ltd. Process for borderless stop in tin via formation
US6348706B1 (en) * 2000-03-20 2002-02-19 Micron Technology, Inc. Method to form etch and/or CMP stop layers
US6989108B2 (en) * 2001-08-30 2006-01-24 Micron Technology, Inc. Etchant gas composition

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3860836A (en) * 1972-12-01 1975-01-14 Honeywell Inc Stabilization of emitter followers
JPS6030153A (ja) * 1983-07-28 1985-02-15 Toshiba Corp 半導体装置
GB8401250D0 (en) * 1984-01-18 1984-02-22 British Telecomm Semiconductor fabrication
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
EP0369336A3 (de) * 1988-11-14 1990-08-22 National Semiconductor Corporation Prozess zur Herstellung von Bipolar- und CMOS-Transistoren auf einem gemeinsamen Substrat
JPH02237135A (ja) * 1989-03-10 1990-09-19 Fujitsu Ltd 半導体装置の製造方法
JP2518435B2 (ja) * 1990-01-29 1996-07-24 ヤマハ株式会社 多層配線形成法

Also Published As

Publication number Publication date
EP0564136A1 (de) 1993-10-06
DE69318880T2 (de) 1998-10-08
EP0564136B1 (de) 1998-06-03
JPH0645330A (ja) 1994-02-18
US5485035A (en) 1996-01-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee