DE69717992T2 - Verfahren zur Herstellung eines JFET Bauelements - Google Patents

Verfahren zur Herstellung eines JFET Bauelements

Info

Publication number
DE69717992T2
DE69717992T2 DE69717992T DE69717992T DE69717992T2 DE 69717992 T2 DE69717992 T2 DE 69717992T2 DE 69717992 T DE69717992 T DE 69717992T DE 69717992 T DE69717992 T DE 69717992T DE 69717992 T2 DE69717992 T2 DE 69717992T2
Authority
DE
Germany
Prior art keywords
diffusion
jfet
manufacturing
channel
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69717992T
Other languages
English (en)
Other versions
DE69717992D1 (de
Inventor
Pierluigi Bellutti
Maurizio Boscardin
Nicola Zorzi
Betta Gian-Franco Dalla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ISTITUTO TRENTINO DI CULTURA T
Original Assignee
ISTITUTO TRENTINO DI CULTURA T
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ISTITUTO TRENTINO DI CULTURA T filed Critical ISTITUTO TRENTINO DI CULTURA T
Publication of DE69717992D1 publication Critical patent/DE69717992D1/de
Application granted granted Critical
Publication of DE69717992T2 publication Critical patent/DE69717992T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Joining Of Glass To Other Materials (AREA)
  • Solid State Image Pick-Up Elements (AREA)
DE69717992T 1997-10-02 1997-10-02 Verfahren zur Herstellung eines JFET Bauelements Expired - Fee Related DE69717992T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97830490A EP0907208B1 (de) 1997-10-02 1997-10-02 Verfahren zur Herstellung eines JFET Bauelements

Publications (2)

Publication Number Publication Date
DE69717992D1 DE69717992D1 (de) 2003-01-30
DE69717992T2 true DE69717992T2 (de) 2003-07-24

Family

ID=8230795

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69717992T Expired - Fee Related DE69717992T2 (de) 1997-10-02 1997-10-02 Verfahren zur Herstellung eines JFET Bauelements

Country Status (3)

Country Link
EP (1) EP0907208B1 (de)
AT (1) ATE230162T1 (de)
DE (1) DE69717992T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004018153B9 (de) 2004-04-08 2012-08-23 Austriamicrosystems Ag Hochvolt-Sperrschicht-Feldeffekttransistor mit retrograder Gatewanne und Verfahren zu dessen Herstellung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4118728A (en) * 1976-09-03 1978-10-03 Fairchild Camera And Instrument Corporation Integrated circuit structures utilizing conductive buried regions
DE2753704C2 (de) * 1977-12-02 1986-11-06 Bernd Prof. Dr. rer.nat 5841 Holzen Höfflinger Verfahren zum gleichzeitigen Herstellen von mittels Feldoxid isolierten CMOS-Schaltungsanordnungen und Bipolartransistoren
JPH05304258A (ja) * 1992-04-28 1993-11-16 Toshiba Corp 半導体装置およびその製造方法
US5296409A (en) * 1992-05-08 1994-03-22 National Semiconductor Corporation Method of making n-channel and p-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process
WO1994019828A1 (en) * 1993-02-25 1994-09-01 National Semiconductor Corporation Fabrication process for cmos device with jfet
EP0676802B1 (de) * 1994-03-31 1998-12-23 STMicroelectronics S.r.l. Verfahren zur Herstellung eines Halbleiterbauteils mit vergrabenem Übergang

Also Published As

Publication number Publication date
DE69717992D1 (de) 2003-01-30
EP0907208A1 (de) 1999-04-07
EP0907208B1 (de) 2002-12-18
ATE230162T1 (de) 2003-01-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee