ATE274240T1 - Verfahren zur herstellung von mosfets mit verbesserten kurz-kanal effekten - Google Patents

Verfahren zur herstellung von mosfets mit verbesserten kurz-kanal effekten

Info

Publication number
ATE274240T1
ATE274240T1 AT94117948T AT94117948T ATE274240T1 AT E274240 T1 ATE274240 T1 AT E274240T1 AT 94117948 T AT94117948 T AT 94117948T AT 94117948 T AT94117948 T AT 94117948T AT E274240 T1 ATE274240 T1 AT E274240T1
Authority
AT
Austria
Prior art keywords
type
gate
devices
channel effects
counterdoped
Prior art date
Application number
AT94117948T
Other languages
English (en)
Inventor
Udo Schwalke
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of ATE274240T1 publication Critical patent/ATE274240T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Amplifiers (AREA)
AT94117948T 1993-12-07 1994-11-14 Verfahren zur herstellung von mosfets mit verbesserten kurz-kanal effekten ATE274240T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16310893A 1993-12-07 1993-12-07

Publications (1)

Publication Number Publication Date
ATE274240T1 true ATE274240T1 (de) 2004-09-15

Family

ID=22588515

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94117948T ATE274240T1 (de) 1993-12-07 1994-11-14 Verfahren zur herstellung von mosfets mit verbesserten kurz-kanal effekten

Country Status (6)

Country Link
US (2) US5932919A (de)
EP (1) EP0657929B1 (de)
JP (1) JPH07202014A (de)
AT (1) ATE274240T1 (de)
DE (1) DE69433949T2 (de)
TW (1) TW268135B (de)

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US5602410A (en) * 1995-08-25 1997-02-11 Siemens Aktiengesellschaft Off-state gate-oxide field reduction in CMOS
DE19612950C1 (de) * 1996-04-01 1997-07-31 Siemens Ag Schaltungsstruktur mit mindestens einem MOS-Transistor und Verfahren zu deren Herstellung
US6140688A (en) * 1998-09-21 2000-10-31 Advanced Micro Devices Inc. Semiconductor device with self-aligned metal-containing gate
US6492688B1 (en) * 1999-03-02 2002-12-10 Siemens Aktiengesellschaft Dual work function CMOS device
KR100434537B1 (ko) * 1999-03-31 2004-06-05 삼성전자주식회사 다공질 실리콘 혹은 다공질 산화 실리콘을 이용한 두꺼운 희생층을 가진 다층 구조 웨이퍼 및 그 제조방법
US6448590B1 (en) * 2000-10-24 2002-09-10 International Business Machines Corporation Multiple threshold voltage FET using multiple work-function gate materials
KR100387259B1 (ko) * 2000-12-29 2003-06-12 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6812529B2 (en) * 2001-03-15 2004-11-02 Micron Technology, Inc. Suppression of cross diffusion and gate depletion
JP4094379B2 (ja) * 2002-08-27 2008-06-04 エルピーダメモリ株式会社 半導体装置及びその製造方法
US6686612B1 (en) 2002-10-01 2004-02-03 T-Ram, Inc. Thyristor-based device adapted to inhibit parasitic current
US6690039B1 (en) 2002-10-01 2004-02-10 T-Ram, Inc. Thyristor-based device that inhibits undesirable conductive channel formation
US7202535B2 (en) * 2005-07-14 2007-04-10 Infineon Technologies Ag Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
US7750416B2 (en) * 2006-05-03 2010-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Modifying work function in PMOS devices by counter-doping
JP5627165B2 (ja) * 2007-04-27 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及び半導体装置の製造方法
US8900954B2 (en) 2011-11-04 2014-12-02 International Business Machines Corporation Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
KR101923763B1 (ko) * 2015-03-13 2018-11-30 매그나칩 반도체 유한회사 레벨 쉬프트 회로 보호용 정전기 방전 보호 회로 및 소자

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US4315781A (en) * 1980-04-23 1982-02-16 Hughes Aircraft Company Method of controlling MOSFET threshold voltage with self-aligned channel stop
JPS5912416A (ja) * 1982-07-14 1984-01-23 Ricoh Co Ltd 多ビ−ム光走査装置
JPS59124161A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd Ｍｉｓ型電界効果半導体装置
US4555842A (en) * 1984-03-19 1985-12-03 At&T Bell Laboratories Method of fabricating VLSI CMOS devices having complementary threshold voltages
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US4908327A (en) * 1988-05-02 1990-03-13 Texas Instruments, Incorporated Counter-doped transistor
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Also Published As

Publication number Publication date
TW268135B (de) 1996-01-11
EP0657929A3 (de) 1997-12-29
EP0657929A2 (de) 1995-06-14
US6380015B1 (en) 2002-04-30
EP0657929B1 (de) 2004-08-18
DE69433949D1 (de) 2004-09-23
DE69433949T2 (de) 2005-09-08
US5932919A (en) 1999-08-03
JPH07202014A (ja) 1995-08-04

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