DE3789350T2 - Herstellungsverfahren zur Ausbildung eines MOS-Transistors durch Selbstausrichtung der Source/Drain-Gebiete. - Google Patents

Herstellungsverfahren zur Ausbildung eines MOS-Transistors durch Selbstausrichtung der Source/Drain-Gebiete.

Info

Publication number
DE3789350T2
DE3789350T2 DE3789350T DE3789350T DE3789350T2 DE 3789350 T2 DE3789350 T2 DE 3789350T2 DE 3789350 T DE3789350 T DE 3789350T DE 3789350 T DE3789350 T DE 3789350T DE 3789350 T2 DE3789350 T2 DE 3789350T2
Authority
DE
Germany
Prior art keywords
alignment
self
manufacturing
source
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3789350T
Other languages
English (en)
Other versions
DE3789350D1 (de
Inventor
Jumpei C O Patent Divi Kumagai
Satoshi C O Patent D Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3789350D1 publication Critical patent/DE3789350D1/de
Publication of DE3789350T2 publication Critical patent/DE3789350T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
DE3789350T 1986-11-07 1987-11-05 Herstellungsverfahren zur Ausbildung eines MOS-Transistors durch Selbstausrichtung der Source/Drain-Gebiete. Expired - Fee Related DE3789350T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61265022A JPS63119574A (ja) 1986-11-07 1986-11-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3789350D1 DE3789350D1 (de) 1994-04-21
DE3789350T2 true DE3789350T2 (de) 1994-07-14

Family

ID=17411492

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3789350T Expired - Fee Related DE3789350T2 (de) 1986-11-07 1987-11-05 Herstellungsverfahren zur Ausbildung eines MOS-Transistors durch Selbstausrichtung der Source/Drain-Gebiete.

Country Status (5)

Country Link
US (1) US4950617A (de)
EP (1) EP0266768B1 (de)
JP (1) JPS63119574A (de)
KR (1) KR910005763B1 (de)
DE (1) DE3789350T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5236851A (en) * 1988-07-14 1993-08-17 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor devices
US5270226A (en) * 1989-04-03 1993-12-14 Matsushita Electric Industrial Co., Ltd. Manufacturing method for LDDFETS using oblique ion implantion technique
US5028556A (en) * 1990-02-16 1991-07-02 Hughes Aircraft Company Process for fabricating radiation hard high voltage devices
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
JP3119902B2 (ja) * 1991-07-16 2000-12-25 三菱電機株式会社 半導体装置およびその製造方法
US5894158A (en) * 1991-09-30 1999-04-13 Stmicroelectronics, Inc. Having halo regions integrated circuit device structure
JPH06232354A (ja) * 1992-12-22 1994-08-19 Internatl Business Mach Corp <Ibm> 静電気保護デバイス
KR0135166B1 (ko) * 1993-07-20 1998-04-25 문정환 반도체장치의 게이트 형성방법
US5393687A (en) * 1993-12-16 1995-02-28 Taiwan Semiconductor Manufacturing Company Method of making buried contact module with multiple poly si layers
FR2716294B1 (fr) * 1994-01-28 1996-05-31 Sgs Thomson Microelectronics Procédé de réalisation d'un transistor bipolaire pour protection d'un circuit intégré contre les décharges électrostatiques.
JPH07321306A (ja) * 1994-03-31 1995-12-08 Seiko Instr Inc 半導体装置およびその製造方法
US5472899A (en) * 1994-03-23 1995-12-05 United Microelectronics Corporation Process for fabrication of an SRAM cell having a highly doped storage node
KR100189964B1 (ko) 1994-05-16 1999-06-01 윤종용 고전압 트랜지스터 및 그 제조방법
US5744372A (en) * 1995-04-12 1998-04-28 National Semiconductor Corporation Fabrication of complementary field-effect transistors each having multi-part channel
US6004854A (en) 1995-07-17 1999-12-21 Micron Technology, Inc. Method of forming CMOS integrated circuitry
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US5985724A (en) * 1996-10-01 1999-11-16 Advanced Micro Devices, Inc. Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
US5963809A (en) * 1997-06-26 1999-10-05 Advanced Micro Devices, Inc. Asymmetrical MOSFET with gate pattern after source/drain formation
US5986314A (en) * 1997-10-08 1999-11-16 Texas Instruments Incorporated Depletion mode MOS capacitor with patterned Vt implants
US6238975B1 (en) * 1998-11-25 2001-05-29 Advanced Micro Devices, Inc. Method for improving electrostatic discharge (ESD) robustness
US6417541B1 (en) * 2001-01-12 2002-07-09 Chartered Semiconductor Manufacturing Ltd ESD protection network with field oxide device and bonding pad
JP5315903B2 (ja) * 2007-10-02 2013-10-16 株式会社リコー 半導体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5188158A (de) * 1975-01-31 1976-08-02
US4028717A (en) * 1975-09-22 1977-06-07 Ibm Corporation Field effect transistor having improved threshold stability
GB1569897A (en) * 1975-12-31 1980-06-25 Ibm Field effect transistor
US4235011A (en) * 1979-03-28 1980-11-25 Honeywell Inc. Semiconductor apparatus
US4294002A (en) * 1979-05-21 1981-10-13 International Business Machines Corp. Making a short-channel FET
FR2461360A1 (fr) * 1979-07-10 1981-01-30 Thomson Csf Procede de fabrication d'un transistor a effet de champ du type dmos a fonctionnement vertical et transistor obtenu par ce procede
US4354307A (en) * 1979-12-03 1982-10-19 Burroughs Corporation Method for mass producing miniature field effect transistors in high density LSI/VLSI chips
JPH0646662B2 (ja) * 1983-12-26 1994-06-15 株式会社日立製作所 半導体装置
JPH0695563B2 (ja) * 1985-02-01 1994-11-24 株式会社日立製作所 半導体装置
CA1242532A (en) * 1984-05-03 1988-09-27 Chong M. Lin Input protection arrangement for vlsi intergrated circuit devices

Also Published As

Publication number Publication date
KR910005763B1 (ko) 1991-08-02
EP0266768B1 (de) 1994-03-16
US4950617A (en) 1990-08-21
JPS63119574A (ja) 1988-05-24
DE3789350D1 (de) 1994-04-21
KR880006786A (ko) 1988-07-25
EP0266768A1 (de) 1988-05-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee