TW230828B - Process for CMOS with self-aligned twin well or triple well - Google Patents

Process for CMOS with self-aligned twin well or triple well

Info

Publication number
TW230828B
TW230828B TW82110162A TW82110162A TW230828B TW 230828 B TW230828 B TW 230828B TW 82110162 A TW82110162 A TW 82110162A TW 82110162 A TW82110162 A TW 82110162A TW 230828 B TW230828 B TW 230828B
Authority
TW
Taiwan
Prior art keywords
well
conductive
implanting
field
mask
Prior art date
Application number
TW82110162A
Other languages
Chinese (zh)
Inventor
Jenn-Chyou Shyu
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW82110162A priority Critical patent/TW230828B/en
Application granted granted Critical
Publication of TW230828B publication Critical patent/TW230828B/en

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A process for CMOS with self-aligned twin well or triple well includes: 1. growing one oxide through hot oxidation on one N-type or P-typesemiconductor substrate, then implanting the doping ion of the firstconductive well; 2. overlaying one Si3N4 layer and through one mask of diffused area todefine field separating area and diffusing area, then implanting thefirst conductive field ion; 3. through one mask of the second conductive well and implanting the dopingion of the second conductive well; 4. simultaneously proceeding field oxidation and driving the doping ion ofthe first and second conductive well, then after one mask of the secondconductive well, and implanting the second conductive well with the secondconductive field ion and the doping ion of adjustable punch throughvoltage of the first conductive channel.
TW82110162A 1993-12-01 1993-12-01 Process for CMOS with self-aligned twin well or triple well TW230828B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW82110162A TW230828B (en) 1993-12-01 1993-12-01 Process for CMOS with self-aligned twin well or triple well

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW82110162A TW230828B (en) 1993-12-01 1993-12-01 Process for CMOS with self-aligned twin well or triple well

Publications (1)

Publication Number Publication Date
TW230828B true TW230828B (en) 1994-09-21

Family

ID=51348599

Family Applications (1)

Application Number Title Priority Date Filing Date
TW82110162A TW230828B (en) 1993-12-01 1993-12-01 Process for CMOS with self-aligned twin well or triple well

Country Status (1)

Country Link
TW (1) TW230828B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985709A (en) * 1996-04-16 1999-11-16 United Microelectronics Corp. Process for fabricating a triple-well structure for semiconductor integrated circuit devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985709A (en) * 1996-04-16 1999-11-16 United Microelectronics Corp. Process for fabricating a triple-well structure for semiconductor integrated circuit devices

Similar Documents

Publication Publication Date Title
EP0312955A3 (en) Semiconductor device having an improved thin film transistor
EP1028473A3 (en) Trench MOS-gated device manufactured with few masks
KR960014718B1 (en) Method of manufacturing transistor
TW332924B (en) Semiconductor
GB1457169A (en) Method for fabricating semiconductor devices using composite mask and ion implantation
EP0889503A3 (en) Method of making a MOS-gated semiconductor device with a single diffusion
EP0403113A3 (en) Field effect semiconductor devices and methods of fabrication thereof
KR960012583B1 (en) Tft (thin film transistor )and the method of manufacturing the same
EP0401786A3 (en) Method of manufacturing a lateral bipolar transistor
ATE274240T1 (en) METHOD FOR PRODUCING MOSFETS WITH IMPROVED SHORT-CHANNEL EFFECTS
EP0239216A3 (en) Cmos compatible bipolar transistor
CA2179246A1 (en) Polysilicon Defined Diffused Resistor
TW230828B (en) Process for CMOS with self-aligned twin well or triple well
EP0865080A3 (en) MOS-gated semiconductor devices
EP0656660A3 (en) BiCMOS process for supporting merged devices
TW302539B (en) Manufacturing method of deep submicron PMOS device shallow junction
JPS52122481A (en) Mos type semiconductor device and its production
JPS5771164A (en) Semiconductor device
JPS57164573A (en) Semiconductor device
TW260809B (en) Process of bipolar junction transistor
TW260820B (en) Process of protecting B punchthrough oxide layer
JPS6481273A (en) Semiconductor memory device
JPS6465875A (en) Thin film transistor and manufacture thereof
EP0817252A3 (en) Method for manufacturing surface channel type P-channel MOS transistor while supressing P-type impurity penetration
TW288176B (en) Process of fabrication CMOS transistor with metal gate

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees