DE69715993D1 - Cache-Speicher mit Verwendung fehlerhaften Ettikettenspeichers - Google Patents
Cache-Speicher mit Verwendung fehlerhaften EttikettenspeichersInfo
- Publication number
- DE69715993D1 DE69715993D1 DE69715993T DE69715993T DE69715993D1 DE 69715993 D1 DE69715993 D1 DE 69715993D1 DE 69715993 T DE69715993 T DE 69715993T DE 69715993 T DE69715993 T DE 69715993T DE 69715993 D1 DE69715993 D1 DE 69715993D1
- Authority
- DE
- Germany
- Prior art keywords
- cache
- cache address
- memory
- tag memory
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP08185932A JP3116827B2 (ja) | 1996-07-16 | 1996-07-16 | キャッシュメモリ制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69715993D1 true DE69715993D1 (de) | 2002-11-07 |
DE69715993T2 DE69715993T2 (de) | 2003-06-12 |
Family
ID=16179409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69715993T Expired - Fee Related DE69715993T2 (de) | 1996-07-16 | 1997-07-15 | Cache-Speicher mit Verwendung fehlerhaften Ettikettenspeichers |
Country Status (5)
Country | Link |
---|---|
US (1) | US5825682A (de) |
EP (1) | EP0823685B1 (de) |
JP (1) | JP3116827B2 (de) |
KR (1) | KR100241483B1 (de) |
DE (1) | DE69715993T2 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10154394A (ja) * | 1996-11-21 | 1998-06-09 | Toshiba Corp | メモリ装置 |
US5907511A (en) * | 1997-12-23 | 1999-05-25 | Lsi Logic Corporation | Electrically selectable redundant components for an embedded DRAM |
US6034433A (en) * | 1997-12-23 | 2000-03-07 | Intel Corporation | Interconnect structure for protecting a transistor gate from charge damage |
US5896331A (en) * | 1997-12-23 | 1999-04-20 | Lsi Logic Corporation | Reprogrammable addressing process for embedded DRAM |
US5901095A (en) * | 1997-12-23 | 1999-05-04 | Lsi Logic Corporation | Reprogrammable address selector for an embedded DRAM |
US5999440A (en) * | 1998-03-30 | 1999-12-07 | Lsi Logic Corporation | Embedded DRAM with noise-protecting substrate isolation well |
US6064588A (en) * | 1998-03-30 | 2000-05-16 | Lsi Logic Corporation | Embedded dram with noise-protected differential capacitor memory cells |
US6005824A (en) * | 1998-06-30 | 1999-12-21 | Lsi Logic Corporation | Inherently compensated clocking circuit for dynamic random access memory |
US5978304A (en) * | 1998-06-30 | 1999-11-02 | Lsi Logic Corporation | Hierarchical, adaptable-configuration dynamic random access memory |
US6748562B1 (en) * | 2000-10-31 | 2004-06-08 | Agilent Technologies, Inc. | Memory tester omits programming of addresses in detected bad columns |
JP3701886B2 (ja) * | 2001-04-27 | 2005-10-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 記憶回路ブロック及びアクセス方法 |
US7240277B2 (en) * | 2003-09-26 | 2007-07-03 | Texas Instruments Incorporated | Memory error detection reporting |
JP2006190402A (ja) * | 2005-01-07 | 2006-07-20 | Renesas Technology Corp | 半導体装置 |
US10020037B2 (en) * | 2007-12-10 | 2018-07-10 | Intel Corporation | Capacity register file |
GB2576005B (en) | 2018-07-31 | 2020-10-07 | Advanced Risc Mach Ltd | Handling guard tag loss |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59207080A (ja) * | 1983-05-10 | 1984-11-24 | Nec Corp | キヤツシユ記憶制御装置 |
AU604101B2 (en) * | 1987-04-13 | 1990-12-06 | Computervision Corporation | High availability cache organization |
JPH035851A (ja) * | 1989-06-01 | 1991-01-11 | Fujitsu Ltd | バッファ記憶装置 |
US5226150A (en) * | 1990-10-01 | 1993-07-06 | Digital Equipment Corporation | Apparatus for suppressing an error report from an address for which an error has already been reported |
US5497347A (en) * | 1994-06-21 | 1996-03-05 | Motorola Inc. | BICMOS cache TAG comparator having redundancy and separate read an compare paths |
US5617347A (en) * | 1995-03-17 | 1997-04-01 | Fujitsu Limited | Cache memory system and method thereof for storing a staged memory item and a cache tag within a single cache array structure |
US5668766A (en) * | 1996-05-16 | 1997-09-16 | Intel Corporation | Method and apparatus for increasing memory read access speed using double-sensing |
-
1996
- 1996-07-16 JP JP08185932A patent/JP3116827B2/ja not_active Expired - Fee Related
-
1997
- 1997-07-15 DE DE69715993T patent/DE69715993T2/de not_active Expired - Fee Related
- 1997-07-15 EP EP97112097A patent/EP0823685B1/de not_active Expired - Lifetime
- 1997-07-16 US US08/895,206 patent/US5825682A/en not_active Expired - Fee Related
- 1997-07-16 KR KR1019970033020A patent/KR100241483B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69715993T2 (de) | 2003-06-12 |
EP0823685B1 (de) | 2002-10-02 |
KR100241483B1 (ko) | 2000-02-01 |
JP3116827B2 (ja) | 2000-12-11 |
JPH1031619A (ja) | 1998-02-03 |
KR980010790A (ko) | 1998-04-30 |
US5825682A (en) | 1998-10-20 |
EP0823685A1 (de) | 1998-02-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |