DE69705553D1 - Überspannungsdetektionsschaltung zur Auswahl der Betriebsart - Google Patents

Überspannungsdetektionsschaltung zur Auswahl der Betriebsart

Info

Publication number
DE69705553D1
DE69705553D1 DE69705553T DE69705553T DE69705553D1 DE 69705553 D1 DE69705553 D1 DE 69705553D1 DE 69705553 T DE69705553 T DE 69705553T DE 69705553 T DE69705553 T DE 69705553T DE 69705553 D1 DE69705553 D1 DE 69705553D1
Authority
DE
Germany
Prior art keywords
node
coupled
transistors
impedance circuit
test mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69705553T
Other languages
English (en)
Other versions
DE69705553T2 (de
Inventor
Takashi Honda
Shinya Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69705553D1 publication Critical patent/DE69705553D1/de
Publication of DE69705553T2 publication Critical patent/DE69705553T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46Test trigger logic
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31701Arrangements for setting the Unit Under Test [UUT] in a test mode
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Amplifiers (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
DE69705553T 1996-01-30 1997-01-27 Überspannungsdetektionsschaltung zur Auswahl der Betriebsart Expired - Lifetime DE69705553T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01423296A JP3609185B2 (ja) 1996-01-30 1996-01-30 信号発生回路及びこれを用いたテストモード設定方法

Publications (2)

Publication Number Publication Date
DE69705553D1 true DE69705553D1 (de) 2001-08-16
DE69705553T2 DE69705553T2 (de) 2002-05-29

Family

ID=11855335

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69705553T Expired - Lifetime DE69705553T2 (de) 1996-01-30 1997-01-27 Überspannungsdetektionsschaltung zur Auswahl der Betriebsart

Country Status (7)

Country Link
US (1) US5786716A (de)
EP (1) EP0788116B1 (de)
JP (1) JP3609185B2 (de)
KR (1) KR100337674B1 (de)
CN (1) CN1158671C (de)
DE (1) DE69705553T2 (de)
TW (1) TW367411B (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1092335C (zh) 1995-08-21 2002-10-09 松下电器产业株式会社 电压检测电路、电源通-断复位电路及半导体装置
JP3288249B2 (ja) * 1997-03-31 2002-06-04 東芝マイクロエレクトロニクス株式会社 パワーオンリセット回路
DE19819265C1 (de) * 1998-04-30 1999-08-19 Micronas Intermetall Gmbh Verfahren zum Parametrieren einer integrierten Schaltungsanordnung und integrierte Schaltungsanordnung hierfür
FR2794867B1 (fr) 1999-06-08 2001-08-10 St Microelectronics Sa Circuit de detection et de memorisation d'une surtension
JP2003132674A (ja) 2001-10-26 2003-05-09 Mitsubishi Electric Corp 半導体記憶装置
JP2005535864A (ja) * 2002-08-16 2005-11-24 ザ・ビーオーシー・グループ・インコーポレーテッド 食品の表面外皮を凍結するための方法及び装置
CN100403034C (zh) * 2003-12-30 2008-07-16 上海贝岭股份有限公司 低功耗低温漂与工艺无关的电压检测电路
CN100356179C (zh) * 2004-09-29 2007-12-19 华为技术有限公司 一种信号发生装置和方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217714A (ja) * 1986-03-19 1987-09-25 Fujitsu Ltd 高電圧検出回路
JPS6337269A (ja) * 1986-08-01 1988-02-17 Fujitsu Ltd モ−ド選定回路
US5019772A (en) * 1989-05-23 1991-05-28 International Business Machines Corporation Test selection techniques
DE59107793D1 (de) * 1991-02-21 1996-06-13 Siemens Ag Regelschaltung für einen Substratvorspannungsgenerator

Also Published As

Publication number Publication date
CN1158671C (zh) 2004-07-21
EP0788116A1 (de) 1997-08-06
TW367411B (en) 1999-08-21
CN1162820A (zh) 1997-10-22
KR970060248A (ko) 1997-08-12
JP3609185B2 (ja) 2005-01-12
JPH09204798A (ja) 1997-08-05
DE69705553T2 (de) 2002-05-29
EP0788116B1 (de) 2001-07-11
US5786716A (en) 1998-07-28
KR100337674B1 (ko) 2002-07-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP