DE69618739D1 - Zur Gewinnung einer Latenz mit einer reduzierten Skalenschaltung fähiger synchroner Halbleiterspeicher - Google Patents

Zur Gewinnung einer Latenz mit einer reduzierten Skalenschaltung fähiger synchroner Halbleiterspeicher

Info

Publication number
DE69618739D1
DE69618739D1 DE69618739T DE69618739T DE69618739D1 DE 69618739 D1 DE69618739 D1 DE 69618739D1 DE 69618739 T DE69618739 T DE 69618739T DE 69618739 T DE69618739 T DE 69618739T DE 69618739 D1 DE69618739 D1 DE 69618739D1
Authority
DE
Germany
Prior art keywords
semiconductor memories
synchronous semiconductor
reduced scaling
capable synchronous
obtain latency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69618739T
Other languages
English (en)
Other versions
DE69618739T2 (de
Inventor
Michinori Sugawara
Manabu Kawaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69618739D1 publication Critical patent/DE69618739D1/de
Publication of DE69618739T2 publication Critical patent/DE69618739T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
DE69618739T 1995-10-20 1996-10-16 Zur Gewinnung einer Latenz mit einer reduzierten Skalenschaltung fähiger synchroner Halbleiterspeicher Expired - Fee Related DE69618739T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29788595A JP3252678B2 (ja) 1995-10-20 1995-10-20 同期式半導体メモリ

Publications (2)

Publication Number Publication Date
DE69618739D1 true DE69618739D1 (de) 2002-03-14
DE69618739T2 DE69618739T2 (de) 2002-10-10

Family

ID=17852375

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69618739T Expired - Fee Related DE69618739T2 (de) 1995-10-20 1996-10-16 Zur Gewinnung einer Latenz mit einer reduzierten Skalenschaltung fähiger synchroner Halbleiterspeicher

Country Status (6)

Country Link
US (1) US5687134A (de)
EP (1) EP0769783B1 (de)
JP (1) JP3252678B2 (de)
KR (1) KR100230120B1 (de)
DE (1) DE69618739T2 (de)
TW (1) TW306057B (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100225947B1 (ko) * 1996-06-27 1999-10-15 김영환 라이트 리커버리 보장 회로
JP2988392B2 (ja) * 1996-08-09 1999-12-13 日本電気株式会社 半導体メモリ集積回路
JP4090088B2 (ja) * 1996-09-17 2008-05-28 富士通株式会社 半導体装置システム及び半導体装置
JPH10228773A (ja) * 1997-02-14 1998-08-25 Hitachi Ltd ダイナミック型ｒａｍ
JP3825862B2 (ja) * 1997-02-27 2006-09-27 株式会社ルネサステクノロジ 同期型ダイナミック型半導体記憶装置
US5933369A (en) * 1997-02-28 1999-08-03 Xilinx, Inc. RAM with synchronous write port using dynamic latches
KR100244456B1 (ko) * 1997-03-22 2000-02-01 김영환 데이터 출력 버퍼를 위한 클럭 조절 장치
KR100265591B1 (ko) * 1997-05-19 2000-11-01 김영환 클럭입력버퍼를분리시킨반도체메모리장치
KR100496785B1 (ko) * 1997-07-24 2005-09-02 삼성전자주식회사 웨이브 파이브 라인의 데이터 구조를 갖는 동기형 반도체 메모리 장치
US6185664B1 (en) * 1997-11-17 2001-02-06 Micron Technology, Inc. Method for providing additional latency for synchronously accessed memory
JP2000076853A (ja) * 1998-06-17 2000-03-14 Mitsubishi Electric Corp 同期型半導体記憶装置
US6629274B1 (en) * 1999-12-21 2003-09-30 Intel Corporation Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer
US6163502A (en) * 1999-12-21 2000-12-19 Advanced Micro Devices, Inc. Clocking to support interface of memory controller to external SRAM
KR100608355B1 (ko) 2004-03-25 2006-08-08 주식회사 하이닉스반도체 메모리 장치의 동작 주파수 변동에 따른 내부 제어 신호의인에이블 구간을 제어하는 장치와 그 방법
US7602906B2 (en) * 2005-08-25 2009-10-13 Microsoft Corporation Cipher for disk encryption
US7577029B2 (en) * 2007-05-04 2009-08-18 Mosaid Technologies Incorporated Multi-level cell access buffer with dual function
JP2007294108A (ja) * 2007-08-10 2007-11-08 Ricoh Co Ltd 半導体集積回路への入力信号の制御方法
KR101103066B1 (ko) * 2010-02-26 2012-01-06 주식회사 하이닉스반도체 반도체 메모리 장치의 어드레스 지연 회로
US8427899B2 (en) * 2010-10-29 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Self-adaptive sensing design

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940008295B1 (ko) * 1989-08-28 1994-09-10 가부시기가이샤 히다찌세이사꾸쇼 반도체메모리
JP2917314B2 (ja) 1989-10-06 1999-07-12 日本電気株式会社 同期式半導体記憶装置
JP2830594B2 (ja) * 1992-03-26 1998-12-02 日本電気株式会社 半導体メモリ装置
KR960004567B1 (ko) * 1994-02-04 1996-04-09 삼성전자주식회사 반도체 메모리 장치의 데이타 출력 버퍼
JP3177094B2 (ja) * 1994-05-31 2001-06-18 富士通株式会社 半導体記憶装置
JP3157681B2 (ja) * 1994-06-27 2001-04-16 日本電気株式会社 論理データ入力ラッチ回路
JP3013714B2 (ja) * 1994-09-28 2000-02-28 日本電気株式会社 半導体記憶装置
JP2697633B2 (ja) * 1994-09-30 1998-01-14 日本電気株式会社 同期型半導体記憶装置

Also Published As

Publication number Publication date
EP0769783A2 (de) 1997-04-23
JPH09120672A (ja) 1997-05-06
US5687134A (en) 1997-11-11
EP0769783A3 (de) 1997-11-12
TW306057B (de) 1997-05-21
KR100230120B1 (ko) 1999-11-15
KR970023373A (ko) 1997-05-30
JP3252678B2 (ja) 2002-02-04
EP0769783B1 (de) 2002-01-23
DE69618739T2 (de) 2002-10-10

Similar Documents

Publication Publication Date Title
DE69618739D1 (de) Zur Gewinnung einer Latenz mit einer reduzierten Skalenschaltung fähiger synchroner Halbleiterspeicher
ATE224700T1 (de) Kosmetisches kissen mit reinigender bräusemittel
FR2733711B1 (fr) Couteau utilitaire
DE69922758D1 (de) Lichtintegrationssystem mit reduzierter dynamischer Schattierung
FR2787868B1 (fr) Capteur solaire pour chauffe-eau
FR2679515B1 (fr) Voilure solaire.
DK0726200T3 (da) Vandafbalanceringsarrangement
KR950012205U (ko) 태양열 온수기
DE29521415U1 (de) Solarkollektor
DE29607366U1 (de) Solarsegel
DE59510684D1 (de) Warmwasserspeicher, insbesondere Elektro-Kleinspeicher
DE19981949D2 (de) Solarelementhalterung
FI103609B1 (fi) Aurinkokeräin
DE69632683D1 (de) Katalytische umwanldung mit mcm-58
KR970007730U (ko) 물 절약형 화석 화분
DE9417286U1 (de) Solarregelung
FI950898A0 (fi) Avkaennare foer konsistensmaetanordningar arbetande enligt vridmomentprincip
LV12154A (lv) Regulejamais hidroparvads
NO950504D0 (no) Vannpute
DE29822555U1 (de) Ausmalvorlage
KR980003160U (ko) 절수 장치
IT1304667B1 (it) Metodo di realizzazione di struttura stratificata e strutturastratificata realizzata secondo il metodo stesso.
DE29707939U1 (de) Solar-Teichinsel
KR970024816U (ko) 난로의 연통을 이용하여 식수를 끓여먹는 방법
KR970017908U (ko) 좋은 물 창조기

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee