DE69529362T2 - System zur Steuerung eines Peripheriebustaktsignals - Google Patents

System zur Steuerung eines Peripheriebustaktsignals

Info

Publication number
DE69529362T2
DE69529362T2 DE69529362T DE69529362T DE69529362T2 DE 69529362 T2 DE69529362 T2 DE 69529362T2 DE 69529362 T DE69529362 T DE 69529362T DE 69529362 T DE69529362 T DE 69529362T DE 69529362 T2 DE69529362 T2 DE 69529362T2
Authority
DE
Germany
Prior art keywords
peripheral bus
master
clock
bus
timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69529362T
Other languages
English (en)
Other versions
DE69529362D1 (de
Inventor
Rita M O'brien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69529362D1 publication Critical patent/DE69529362D1/de
Application granted granted Critical
Publication of DE69529362T2 publication Critical patent/DE69529362T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE69529362T 1994-04-28 1995-03-02 System zur Steuerung eines Peripheriebustaktsignals Expired - Lifetime DE69529362T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US23481994A 1994-04-28 1994-04-28

Publications (2)

Publication Number Publication Date
DE69529362D1 DE69529362D1 (de) 2003-02-20
DE69529362T2 true DE69529362T2 (de) 2003-10-30

Family

ID=22882960

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69529362T Expired - Lifetime DE69529362T2 (de) 1994-04-28 1995-03-02 System zur Steuerung eines Peripheriebustaktsignals

Country Status (5)

Country Link
US (1) US5628019A (de)
EP (1) EP0679982B1 (de)
JP (1) JP3633998B2 (de)
AT (1) ATE231254T1 (de)
DE (1) DE69529362T2 (de)

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US5678065A (en) * 1994-09-19 1997-10-14 Advanced Micro Devices, Inc. Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency
DE69522633T2 (de) * 1994-10-19 2002-07-04 Advanced Micro Devices Inc Integrierte Prozessorsysteme für tragbare Informationsgeräte
US5805923A (en) * 1995-05-26 1998-09-08 Sony Corporation Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used
JP2974950B2 (ja) * 1995-10-26 1999-11-10 インターナショナル・ビジネス・マシーンズ・コーポレイション 情報処理システム
US5907688A (en) * 1996-06-28 1999-05-25 Intel Corporation Smart arbitration for non-symmetric data streams
US6079022A (en) * 1996-10-11 2000-06-20 Intel Corporation Method and apparatus for dynamically adjusting the clock speed of a bus depending on bus activity
JP3592547B2 (ja) * 1998-09-04 2004-11-24 株式会社ルネサステクノロジ 情報処理装置および信号転送方法
US6763478B1 (en) * 2000-10-24 2004-07-13 Dell Products, L.P. Variable clock cycle for processor, bus and components for power management in an information handling system
US6694441B1 (en) * 2000-11-15 2004-02-17 Koninklijke Philips Electronics N.V. Power management method and arrangement for bus-coupled circuit blocks
KR100710942B1 (ko) * 2001-04-25 2007-04-24 엘지전자 주식회사 피씨아이 버스에 연결 접속된 디바이스 클럭 제어장치
JP4733877B2 (ja) * 2001-08-15 2011-07-27 富士通セミコンダクター株式会社 半導体装置
JP3447725B2 (ja) * 2001-10-23 2003-09-16 沖電気工業株式会社 競合調停装置
TW533357B (en) * 2001-12-14 2003-05-21 Via Tech Inc Method of hot switching the data transmission rate of bus
JP3835328B2 (ja) 2002-03-27 2006-10-18 ブラザー工業株式会社 メモリ制御装置
US7281148B2 (en) * 2004-03-26 2007-10-09 Intel Corporation Power managed busses and arbitration
US7606960B2 (en) * 2004-03-26 2009-10-20 Intel Corporation Apparatus for adjusting a clock frequency of a variable speed bus
KR100630693B1 (ko) * 2004-07-28 2006-10-02 삼성전자주식회사 소비 전력을 절감시키는 버스 중재 시스템 및 방법
JP2008542932A (ja) 2005-06-10 2008-11-27 フリースケール セミコンダクター インコーポレイテッド 媒体アクセス制御装置及び方法
US8223910B2 (en) * 2005-06-10 2012-07-17 Freescale Semiconductor, Inc. Method and device for frame synchronization
JP2007058279A (ja) * 2005-08-22 2007-03-08 Oki Electric Ind Co Ltd パワーダウン移行システム
JP4917649B2 (ja) * 2006-10-31 2012-04-18 フリースケール セミコンダクター インコーポレイテッド ネットワークおよび該ネットワークにおけるノードの時間基準を設定する方法
JP5277533B2 (ja) * 2006-11-15 2013-08-28 ヤマハ株式会社 デジタル信号処理装置
CN101329589B (zh) * 2008-07-28 2011-04-27 北京中星微电子有限公司 一种低功耗读写寄存器的控制系统及方法
US10817043B2 (en) * 2011-07-26 2020-10-27 Nvidia Corporation System and method for entering and exiting sleep mode in a graphics subsystem
US10503674B2 (en) 2016-02-03 2019-12-10 Samsung Electronics Co., Ltd. Semiconductor device including a clock source for generating a clock signal and a clock control circuit for controlling the clock source in hardware, a semiconductor system including the semiconductor device, and a method of operating the semiconductor device
JP6906369B2 (ja) * 2017-05-29 2021-07-21 キヤノン株式会社 コンピュータシステム、その制御方法、及びプログラム
US11144358B1 (en) 2018-12-06 2021-10-12 Pure Storage, Inc. Asynchronous arbitration of shared resources

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381552A (en) * 1978-12-08 1983-04-26 Motorola Inc. Stanby mode controller utilizing microprocessor
US4748559A (en) * 1979-08-09 1988-05-31 Motorola, Inc. Apparatus for reducing power consumed by a static microprocessor
JPS58127262A (ja) * 1982-01-25 1983-07-29 Toshiba Corp マイクロコンピユ−タ
JPS59200327A (ja) * 1983-04-26 1984-11-13 Nec Corp 周辺装置の制御方式
JPS61156338A (ja) * 1984-12-27 1986-07-16 Toshiba Corp マルチプロセツサシステム
US5150467A (en) * 1987-09-04 1992-09-22 Digital Equipment Corporation Method and apparatus for suspending and restarting a bus cycle
DE68925615T2 (de) * 1988-11-10 1996-09-12 Motorola Inc Digitalrechnersystem mit Niederstromverbrauchmodus
US5167024A (en) * 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
US5263172A (en) * 1990-04-16 1993-11-16 International Business Machines Corporation Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals
US5341508A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems Inc. Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus
US5392422A (en) * 1992-06-26 1995-02-21 Sun Microsystems, Inc. Source synchronized metastable free bus
US5339395A (en) * 1992-09-17 1994-08-16 Delco Electronics Corporation Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system

Also Published As

Publication number Publication date
DE69529362D1 (de) 2003-02-20
JPH07302132A (ja) 1995-11-14
EP0679982A1 (de) 1995-11-02
EP0679982B1 (de) 2003-01-15
JP3633998B2 (ja) 2005-03-30
US5628019A (en) 1997-05-06
ATE231254T1 (de) 2003-02-15

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