ATE412217T1 - Regeln einer datenübertragungszeit - Google Patents

Regeln einer datenübertragungszeit

Info

Publication number
ATE412217T1
ATE412217T1 AT99949955T AT99949955T ATE412217T1 AT E412217 T1 ATE412217 T1 AT E412217T1 AT 99949955 T AT99949955 T AT 99949955T AT 99949955 T AT99949955 T AT 99949955T AT E412217 T1 ATE412217 T1 AT E412217T1
Authority
AT
Austria
Prior art keywords
bus
indication
circuit
data
rules
Prior art date
Application number
AT99949955T
Other languages
English (en)
Inventor
Kenneth Holland
David Lee
Susan Meredith
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE412217T1 publication Critical patent/ATE412217T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
AT99949955T 1998-12-29 1999-09-29 Regeln einer datenübertragungszeit ATE412217T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/222,213 US6078980A (en) 1998-12-29 1998-12-29 Regulating a data transfer time

Publications (1)

Publication Number Publication Date
ATE412217T1 true ATE412217T1 (de) 2008-11-15

Family

ID=22831339

Family Applications (1)

Application Number Title Priority Date Filing Date
AT99949955T ATE412217T1 (de) 1998-12-29 1999-09-29 Regeln einer datenübertragungszeit

Country Status (8)

Country Link
US (1) US6078980A (de)
EP (1) EP1141832B1 (de)
JP (1) JP3686834B2 (de)
AT (1) ATE412217T1 (de)
AU (1) AU6272299A (de)
DE (1) DE69939782D1 (de)
HK (1) HK1038088A1 (de)
WO (1) WO2000039682A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2790892A1 (fr) * 1999-03-12 2000-09-15 Canon Kk Procede et dispositif de controle de la synchronisation entre deux bus de communication serie d'un reseau
US7107383B1 (en) * 2000-05-03 2006-09-12 Broadcom Corporation Method and system for multi-channel transfer of data and control information
US6346828B1 (en) 2000-06-30 2002-02-12 Intel Corporation Method and apparatus for pulsed clock tri-state control
EP1623331A1 (de) 2003-05-07 2006-02-08 Koninklijke Philips Electronics N.V. Verarbeitungssystem und verfahren zur datenübertragung
US7269672B2 (en) * 2003-08-19 2007-09-11 Fujitsu Limited Bus system design method, bus system, and device unit
US8208522B2 (en) * 2008-03-07 2012-06-26 Nokia Corporation System and methods for receiving OFDM symbols having timing and frequency offsets
TWI433163B (zh) * 2009-12-23 2014-04-01 Mstar Semiconductor Inc 記憶體控制器及其控制方法
JP6512640B1 (ja) 2017-10-19 2019-05-15 Ｎｅｃプラットフォームズ株式会社 非同期ｆｉｆｏ回路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717046A (en) * 1980-07-03 1982-01-28 Fujitsu Ltd Skew compensating circuit
JPS62194755A (ja) * 1986-02-21 1987-08-27 Nippon Telegr & Teleph Corp <Ntt> スキユ−補償方式
US4949249A (en) * 1987-04-10 1990-08-14 Prime Computer, Inc. Clock skew avoidance technique for pipeline processors
US5463739A (en) * 1992-12-22 1995-10-31 International Business Machines Corporation Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold
US5625805A (en) * 1994-06-30 1997-04-29 Digital Equipment Corporation Clock architecture for synchronous system bus which regulates and adjusts clock skew
US5717932A (en) * 1994-11-04 1998-02-10 Texas Instruments Incorporated Data transfer interrupt pacing
US5623649A (en) * 1995-10-31 1997-04-22 Texas Instruments Incorporated Method and apparatus for passing a bus clock signal from a computer to an expansion chassis
US5778194A (en) * 1996-04-08 1998-07-07 Symbios, Inc. Method and apparatus for measuring performance of a computer bus
US5894559A (en) * 1996-08-15 1999-04-13 Advanced Micro Devices, Inc. System for selectively reducing capture effect in a network station by increasing delay time after a predetermined number of consecutive successful transmissions
US5872959A (en) * 1996-09-10 1999-02-16 Lsi Logic Corporation Method and apparatus for parallel high speed data transfer
US5898895A (en) * 1996-10-10 1999-04-27 Unisys Corporation System and method for controlling data transmission rates between circuits in different clock domains via selectable acknowledge signal timing

Also Published As

Publication number Publication date
JP3686834B2 (ja) 2005-08-24
HK1038088A1 (en) 2002-03-01
DE69939782D1 (de) 2008-12-04
EP1141832B1 (de) 2008-10-22
EP1141832A1 (de) 2001-10-10
WO2000039682A1 (en) 2000-07-06
AU6272299A (en) 2000-07-31
JP2002533832A (ja) 2002-10-08
US6078980A (en) 2000-06-20

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Legal Events

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