JPS5717046A - Skew compensating circuit - Google Patents

Skew compensating circuit

Info

Publication number
JPS5717046A
JPS5717046A JP9085580A JP9085580A JPS5717046A JP S5717046 A JPS5717046 A JP S5717046A JP 9085580 A JP9085580 A JP 9085580A JP 9085580 A JP9085580 A JP 9085580A JP S5717046 A JPS5717046 A JP S5717046A
Authority
JP
Japan
Prior art keywords
circuit
signal
control device
delay
skew
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9085580A
Other languages
Japanese (ja)
Inventor
Toshiki Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9085580A priority Critical patent/JPS5717046A/en
Publication of JPS5717046A publication Critical patent/JPS5717046A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To ensure a highly efficient transmission of asynchronous information, by adding a skew compensating circuit to each control device and giving a proper delay time to each control device to realize a high-speed operation. CONSTITUTION:In case a device 2 to be controlled requests a data to a control device 1, the signal is set to the terminal S of an FF circuit 6. The circuit 6 transmits the request signal 8, and the signal 8 is sent to the device 1 via a cable 3. The device 1 transmits the data to a bus line 9 and at the same time sends the answer signal 4 to delaying circuits 5-1, 5-2 and 5-3 connected in series to each other. These delaying circuits are connected to contacts C, B and A of a switch circuit 11. The delay of the contact A is maximum, and the delay of the contact C is minimum. Thus the delay time for compensation of skew can be selected through a circuit 11.
JP9085580A 1980-07-03 1980-07-03 Skew compensating circuit Pending JPS5717046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9085580A JPS5717046A (en) 1980-07-03 1980-07-03 Skew compensating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9085580A JPS5717046A (en) 1980-07-03 1980-07-03 Skew compensating circuit

Publications (1)

Publication Number Publication Date
JPS5717046A true JPS5717046A (en) 1982-01-28

Family

ID=14010177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9085580A Pending JPS5717046A (en) 1980-07-03 1980-07-03 Skew compensating circuit

Country Status (1)

Country Link
JP (1) JPS5717046A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000039682A1 (en) * 1998-12-29 2000-07-06 Intel Corporation Regulating a data transfer time
US8582670B2 (en) 2009-05-08 2013-11-12 Fujitsu Limited Receiving apparatus, transmitting-receiving apparatus, and transmission system method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000039682A1 (en) * 1998-12-29 2000-07-06 Intel Corporation Regulating a data transfer time
US8582670B2 (en) 2009-05-08 2013-11-12 Fujitsu Limited Receiving apparatus, transmitting-receiving apparatus, and transmission system method therefor

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