DE69524992D1 - Verfahren zur Isolierung von Teilen einer Halbleitervorrichtung - Google Patents
Verfahren zur Isolierung von Teilen einer HalbleitervorrichtungInfo
- Publication number
- DE69524992D1 DE69524992D1 DE69524992T DE69524992T DE69524992D1 DE 69524992 D1 DE69524992 D1 DE 69524992D1 DE 69524992 T DE69524992 T DE 69524992T DE 69524992 T DE69524992 T DE 69524992T DE 69524992 D1 DE69524992 D1 DE 69524992D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor device
- isolating parts
- isolating
- parts
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940012841A KR100303438B1 (ko) | 1994-06-08 | 1994-06-08 | 반도체장치의소자분리방법 |
KR1019940040685A KR0141171B1 (ko) | 1994-12-31 | 1994-12-31 | 보이드를 이용한 반도체 소자분리 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69524992D1 true DE69524992D1 (de) | 2002-02-21 |
DE69524992T2 DE69524992T2 (de) | 2002-06-27 |
Family
ID=26630425
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69524992T Expired - Lifetime DE69524992T2 (de) | 1994-06-08 | 1995-06-06 | Verfahren zur Isolierung von Teilen einer Halbleitervorrichtung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5641705A (de) |
EP (1) | EP0687001B1 (de) |
JP (1) | JP3468920B2 (de) |
CN (1) | CN1059517C (de) |
DE (1) | DE69524992T2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8802537B1 (en) * | 2005-07-27 | 2014-08-12 | Spansion Llc | System and method for improving reliability in a semiconductor device |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4663832A (en) * | 1984-06-29 | 1987-05-12 | International Business Machines Corporation | Method for improving the planarity and passivation in a semiconductor isolation trench arrangement |
US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
KR880008448A (ko) * | 1986-12-17 | 1988-08-31 | 강진구 | 측면 격리 소자 분리방법 |
DE3865058D1 (de) * | 1987-02-24 | 1991-10-31 | Sgs Thomson Microelectronics | Isolationsverfahren mit einer durch eine schutzschicht aus oxid geschuetzten zwischenschicht. |
JP2722518B2 (ja) * | 1988-09-02 | 1998-03-04 | ソニー株式会社 | 半導体装置の製造方法 |
KR930004125B1 (ko) * | 1990-08-18 | 1993-05-20 | 삼성전자 주식회사 | 반도체장치의 소자 분리방법 |
US5308784A (en) * | 1991-10-02 | 1994-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method for making the same |
KR950004972B1 (ko) * | 1992-10-13 | 1995-05-16 | 현대전자산업주식회사 | 반도체 장치의 필드산화막 형성 방법 |
US5393692A (en) * | 1993-07-28 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Recessed side-wall poly plugged local oxidation |
-
1995
- 1995-06-06 EP EP95303890A patent/EP0687001B1/de not_active Expired - Lifetime
- 1995-06-06 DE DE69524992T patent/DE69524992T2/de not_active Expired - Lifetime
- 1995-06-06 US US08/470,914 patent/US5641705A/en not_active Expired - Lifetime
- 1995-06-08 JP JP16830195A patent/JP3468920B2/ja not_active Expired - Lifetime
- 1995-06-08 CN CN95107354A patent/CN1059517C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0687001A3 (de) | 1997-05-02 |
JPH07335743A (ja) | 1995-12-22 |
JP3468920B2 (ja) | 2003-11-25 |
US5641705A (en) | 1997-06-24 |
DE69524992T2 (de) | 2002-06-27 |
CN1123467A (zh) | 1996-05-29 |
EP0687001B1 (de) | 2002-01-16 |
EP0687001A2 (de) | 1995-12-13 |
CN1059517C (zh) | 2000-12-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |