DE69520340T2 - Apparat und Methode zur Chipausbeuteermittlung - Google Patents

Apparat und Methode zur Chipausbeuteermittlung

Info

Publication number
DE69520340T2
DE69520340T2 DE69520340T DE69520340T DE69520340T2 DE 69520340 T2 DE69520340 T2 DE 69520340T2 DE 69520340 T DE69520340 T DE 69520340T DE 69520340 T DE69520340 T DE 69520340T DE 69520340 T2 DE69520340 T2 DE 69520340T2
Authority
DE
Germany
Prior art keywords
chip yield
determining chip
determining
yield
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69520340T
Other languages
English (en)
Other versions
DE69520340D1 (de
Inventor
Takao Kamatsuzaki
Yoichi Miyai
Hideyuki Fukuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69520340D1 publication Critical patent/DE69520340D1/de
Publication of DE69520340T2 publication Critical patent/DE69520340T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69520340T 1994-12-09 1995-12-11 Apparat und Methode zur Chipausbeuteermittlung Expired - Lifetime DE69520340T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30603594A JP3986571B2 (ja) 1994-12-09 1994-12-09 歩留り予測装置とその方法

Publications (2)

Publication Number Publication Date
DE69520340D1 DE69520340D1 (de) 2001-04-19
DE69520340T2 true DE69520340T2 (de) 2001-07-12

Family

ID=17952288

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69520340T Expired - Lifetime DE69520340T2 (de) 1994-12-09 1995-12-11 Apparat und Methode zur Chipausbeuteermittlung

Country Status (5)

Country Link
US (1) US5754432A (de)
EP (1) EP0718880B1 (de)
JP (1) JP3986571B2 (de)
KR (1) KR100359599B1 (de)
DE (1) DE69520340T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3364109B2 (ja) * 1997-04-18 2003-01-08 松下電器産業株式会社 集積回路装置の歩留まり推定方法
US6070004A (en) * 1997-09-25 2000-05-30 Siemens Aktiengesellschaft Method of maximizing chip yield for semiconductor wafers
US6044208A (en) * 1998-04-30 2000-03-28 International Business Machines Corporation Incremental critical area computation for VLSI yield prediction
US6247853B1 (en) * 1998-05-26 2001-06-19 International Business Machines Corporation Incremental method for critical area and critical region computation of via blocks
US6367040B1 (en) * 1999-01-11 2002-04-02 Siemens Aktiengesellschaft System and method for determining yield impact for semiconductor devices
JP4080087B2 (ja) 1999-02-01 2008-04-23 株式会社日立製作所 分析方法，分析システム及び分析装置
US6707936B1 (en) 1999-04-16 2004-03-16 Texas Instruments Incorporated Method and apparatus for predicting device yield from a semiconductor wafer
US6449749B1 (en) * 1999-11-18 2002-09-10 Pdf Solutions, Inc. System and method for product yield prediction
JP4170569B2 (ja) * 2000-06-02 2008-10-22 大日本印刷株式会社 基板選択装置
JP4357134B2 (ja) 2001-03-29 2009-11-04 株式会社日立製作所 検査システムと検査装置と半導体デバイスの製造方法及び検査プログラム
JP4126189B2 (ja) * 2002-04-10 2008-07-30 株式会社日立ハイテクノロジーズ 検査条件設定プログラム、検査装置および検査システム
US6909931B2 (en) * 2002-06-04 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for estimating microelectronic fabrication product yield
US6996790B2 (en) * 2003-01-30 2006-02-07 Synopsys, Inc. System and method for generating a two-dimensional yield map for a full layout
US9002497B2 (en) 2003-07-03 2015-04-07 Kla-Tencor Technologies Corp. Methods and systems for inspection of wafers and reticles using designer intent data
US7725849B2 (en) * 2004-10-01 2010-05-25 Mentor Graphics Corporation Feature failure correlation
JP4718914B2 (ja) * 2005-06-28 2011-07-06 株式会社東芝 半導体集積回路の設計支援システム、半導体集積回路の設計方法、半導体集積回路の設計支援プログラム、半導体集積回路の製造方法
US7544578B2 (en) 2007-01-03 2009-06-09 International Business Machines Corporation Structure and method for stochastic integrated circuit personalization
US7752580B2 (en) * 2007-07-26 2010-07-06 International Business Machines Corporation Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique
JP4893778B2 (ja) * 2009-05-21 2012-03-07 大日本印刷株式会社 描画用基板の供給方法および基板選択装置
US8276102B2 (en) 2010-03-05 2012-09-25 International Business Machines Corporation Spatial correlation-based estimation of yield of integrated circuits
US20130218518A1 (en) * 2012-02-21 2013-08-22 International Business Machines Corporation Automated, three dimensional mappable environmental sampling system and methods of use
KR20200122673A (ko) * 2019-04-18 2020-10-28 삼성전자주식회사 패턴 디자인 및 상기 패턴 디자인을 검사하기 위한 방법

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4840376B1 (de) 1969-01-09 1973-11-30
DE2240654A1 (de) * 1971-09-22 1973-03-29 Ibm Verfahren in einem herstellungsprozess fuer monolithisch integrierte schaltungen
US3751647A (en) * 1971-09-22 1973-08-07 Ibm Semiconductor and integrated circuit device yield modeling
US3983479A (en) * 1975-07-23 1976-09-28 International Business Machines Corporation Electrical defect monitor structure
DE3070721D1 (en) * 1980-12-18 1985-07-04 Ibm Process for inspecting and automatically classifying objects presenting configurations with dimensional tolerances and variable rejecting criteria depending on placement, apparatus and circuits therefor
US4763289A (en) * 1985-12-31 1988-08-09 International Business Machines Corporation Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits
US4835466A (en) * 1987-02-06 1989-05-30 Fairchild Semiconductor Corporation Apparatus and method for detecting spot defects in integrated circuits
US5287290A (en) * 1989-03-10 1994-02-15 Fujitsu Limited Method and apparatus for checking a mask pattern
US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
JP2679500B2 (ja) * 1990-12-17 1997-11-19 モトローラ・インコーポレイテッド 総合的なシステム歩留りを計算するための方法
US5282140A (en) * 1992-06-24 1994-01-25 Intel Corporation Particle flux shadowing for three-dimensional topography simulation
US5497381A (en) * 1993-10-15 1996-03-05 Analog Devices, Inc. Bitstream defect analysis method for integrated circuits
JPH07306848A (ja) * 1994-05-16 1995-11-21 Matsushita Electron Corp 歩留まり推定装置
US5539652A (en) * 1995-02-07 1996-07-23 Hewlett-Packard Company Method for manufacturing test simulation in electronic circuit design
US5598341A (en) * 1995-03-10 1997-01-28 Advanced Micro Devices, Inc. Real-time in-line defect disposition and yield forecasting system
US5649169A (en) * 1995-06-20 1997-07-15 Advanced Micro Devices, Inc. Method and system for declustering semiconductor defect data

Also Published As

Publication number Publication date
JP3986571B2 (ja) 2007-10-03
EP0718880A2 (de) 1996-06-26
KR960026522A (ko) 1996-07-22
EP0718880B1 (de) 2001-03-14
JPH08162510A (ja) 1996-06-21
DE69520340D1 (de) 2001-04-19
KR100359599B1 (ko) 2003-01-24
EP0718880A3 (de) 1997-02-05
US5754432A (en) 1998-05-19

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Legal Events

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