DE69519056D1 - Zuverlässigkeitstestverfahren für Halbleiternutanordnungen - Google Patents

Zuverlässigkeitstestverfahren für Halbleiternutanordnungen

Info

Publication number
DE69519056D1
DE69519056D1 DE69519056T DE69519056T DE69519056D1 DE 69519056 D1 DE69519056 D1 DE 69519056D1 DE 69519056 T DE69519056 T DE 69519056T DE 69519056 T DE69519056 T DE 69519056T DE 69519056 D1 DE69519056 D1 DE 69519056D1
Authority
DE
Germany
Prior art keywords
test method
reliability test
groove arrangements
semiconductor groove
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69519056T
Other languages
English (en)
Other versions
DE69519056T2 (de
Inventor
Fwu-Iuan Hsieh
Calvin K Choi
William H Cook
Lih-Ying Ching
Mike F Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of DE69519056D1 publication Critical patent/DE69519056D1/de
Application granted granted Critical
Publication of DE69519056T2 publication Critical patent/DE69519056T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69519056T 1994-06-30 1995-06-19 Zuverlässigkeitstestverfahren für Halbleiternutanordnungen Expired - Fee Related DE69519056T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/268,755 US5486772A (en) 1994-06-30 1994-06-30 Reliability test method for semiconductor trench devices

Publications (2)

Publication Number Publication Date
DE69519056D1 true DE69519056D1 (de) 2000-11-16
DE69519056T2 DE69519056T2 (de) 2001-03-08

Family

ID=23024326

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69519056T Expired - Fee Related DE69519056T2 (de) 1994-06-30 1995-06-19 Zuverlässigkeitstestverfahren für Halbleiternutanordnungen
DE0690311T Pending DE690311T1 (de) 1994-06-30 1995-06-19 Zuverlässigkeitstestverfahren für Halbleiternutanordnungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE0690311T Pending DE690311T1 (de) 1994-06-30 1995-06-19 Zuverlässigkeitstestverfahren für Halbleiternutanordnungen

Country Status (5)

Country Link
US (1) US5486772A (de)
EP (1) EP0690311B1 (de)
JP (1) JP3921248B2 (de)
KR (1) KR0161322B1 (de)
DE (2) DE69519056T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689128A (en) * 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
US5821583A (en) * 1996-03-06 1998-10-13 Siliconix Incorporated Trenched DMOS transistor with lightly doped tub
DE19610065A1 (de) * 1996-03-14 1997-09-18 Siemens Ag Verfahren zur Abschätzung der Lebensdauer eines Leistungshalbleiter-Bauelements
WO1998045719A1 (en) 1997-04-04 1998-10-15 University Of Florida Method for testing and diagnosing mos transistors
US6255707B1 (en) 1998-08-24 2001-07-03 Lucent Technologies, Inc. Semiconductor laser reliability test structure and method
US6348808B1 (en) * 1999-06-25 2002-02-19 Lsi Logic Corporation Mobile ionic contamination detection in manufacture of semiconductor devices
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US7298159B1 (en) * 2005-07-07 2007-11-20 National Semiconductor Corporation Method of measuring the leakage current of a deep trench isolation structure
KR100732762B1 (ko) * 2005-10-26 2007-06-27 주식회사 하이닉스반도체 리세스게이트를 갖는 반도체소자의 테스트패턴 및 그제조방법
US7256605B2 (en) * 2005-11-14 2007-08-14 Semiconductor Components Industries, L.L.C. Diagnostic circuit and method therefor
JP4776368B2 (ja) * 2005-12-20 2011-09-21 矢崎総業株式会社 電力供給回路のオン故障検出装置
JP4593526B2 (ja) * 2006-06-09 2010-12-08 株式会社デンソー 半導体装置のスクリーニング方法および半導体装置
JP4927164B2 (ja) * 2007-04-12 2012-05-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2011071174A (ja) * 2009-09-24 2011-04-07 Renesas Electronics Corp 半導体装置、及び半導体装置の特性劣化検出方法
CN102568578A (zh) * 2010-12-08 2012-07-11 旺宏电子股份有限公司 半导体存储装置及其测试及控制方法
CN102737726A (zh) * 2011-04-13 2012-10-17 旺宏电子股份有限公司 存储阵列局部位线缺陷的检测方法
CN103887202B (zh) * 2014-03-24 2016-08-17 上海华力微电子有限公司 监测方法
CN104483615B (zh) * 2014-12-24 2017-10-24 上海华虹宏力半导体制造有限公司 沟槽栅mos器件缺陷验证方法
CN104575614A (zh) * 2015-02-10 2015-04-29 武汉新芯集成电路制造有限公司 一种存储单元失效筛选的方法
CN107078061B (zh) * 2015-03-16 2020-07-10 富士电机株式会社 半导体装置的制造方法
US10215795B1 (en) * 2018-04-13 2019-02-26 Infineon Technologies Ag Three level gate monitoring
CN112599436B (zh) * 2020-12-10 2022-07-05 泉芯集成电路制造(济南)有限公司 一种侦测结构、及sti异常孔洞的侦测方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US826875A (en) * 1906-04-16 1906-07-24 Isaac E Palmer Thread-guide.
DE3173901D1 (en) * 1981-10-28 1986-04-03 Ibm Process for characterising the reliability behaviour of bipolar semiconductor devices
US4542340A (en) * 1982-12-30 1985-09-17 Ibm Corporation Testing method and structure for leakage current characterization in the manufacture of dynamic RAM cells
US4835458A (en) * 1987-11-09 1989-05-30 Intel Corporation Signature analysis technique for defect characterization of CMOS static RAM cell failures
US5072266A (en) 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5239270A (en) * 1992-02-24 1993-08-24 National Semiconductor Corporation Wafer level reliability contact test structure and method

Also Published As

Publication number Publication date
EP0690311A2 (de) 1996-01-03
EP0690311A3 (de) 1997-06-18
US5486772A (en) 1996-01-23
DE69519056T2 (de) 2001-03-08
JPH08181180A (ja) 1996-07-12
DE690311T1 (de) 1996-09-19
KR960001769A (ko) 1996-01-25
KR0161322B1 (ko) 1999-03-20
EP0690311B1 (de) 2000-10-11
JP3921248B2 (ja) 2007-05-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee