DE69513899T2 - Verfahren zur Herstellung einer Oxidschicht in der Halbleitertechnik - Google Patents

Verfahren zur Herstellung einer Oxidschicht in der Halbleitertechnik

Info

Publication number
DE69513899T2
DE69513899T2 DE69513899T DE69513899T DE69513899T2 DE 69513899 T2 DE69513899 T2 DE 69513899T2 DE 69513899 T DE69513899 T DE 69513899T DE 69513899 T DE69513899 T DE 69513899T DE 69513899 T2 DE69513899 T2 DE 69513899T2
Authority
DE
Germany
Prior art keywords
layer
semiconductor body
oxide
gate
heavily
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69513899T
Other languages
English (en)
Other versions
DE69513899D1 (de
Inventor
H Jim Fulford
Mark Gardner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69513899D1 publication Critical patent/DE69513899D1/de
Publication of DE69513899T2 publication Critical patent/DE69513899T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/981Utilizing varying dielectric thickness
DE69513899T 1994-07-26 1995-07-13 Verfahren zur Herstellung einer Oxidschicht in der Halbleitertechnik Expired - Lifetime DE69513899T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/280,416 US5498577A (en) 1994-07-26 1994-07-26 Method for fabricating thin oxides for a semiconductor technology

Publications (2)

Publication Number Publication Date
DE69513899D1 DE69513899D1 (de) 2000-01-20
DE69513899T2 true DE69513899T2 (de) 2000-06-21

Family

ID=23072985

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69513899T Expired - Lifetime DE69513899T2 (de) 1994-07-26 1995-07-13 Verfahren zur Herstellung einer Oxidschicht in der Halbleitertechnik

Country Status (5)

Country Link
US (1) US5498577A (de)
EP (1) EP0696051B1 (de)
JP (2) JPH08172138A (de)
AT (1) ATE187844T1 (de)
DE (1) DE69513899T2 (de)

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JP3305901B2 (ja) * 1994-12-14 2002-07-24 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法
US5869405A (en) * 1996-01-03 1999-02-09 Micron Technology, Inc. In situ rapid thermal etch and rapid thermal oxidation
US5741737A (en) * 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
JP3593825B2 (ja) * 1996-11-08 2004-11-24 ソニー株式会社 半導体装置及びその製造方法、並びに固体撮像素子の製造方法
US6461984B1 (en) * 1997-03-18 2002-10-08 Korea Advanced Institute Of Science & Technology Semiconductor device using N2O plasma oxide and a method of fabricating the same
US5904542A (en) * 1997-03-26 1999-05-18 Advanced Micro Devices, Inc. Performing a semiconductor fabrication sequence within a common chamber and without opening the chamber beginning with forming a field dielectric and concluding with a gate dielectric
US5937308A (en) * 1997-03-26 1999-08-10 Advanced Micro Devices, Inc. Semiconductor trench isolation structure formed substantially within a single chamber
US5891793A (en) * 1997-04-04 1999-04-06 Advanced Micro Devices, Inc. Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation
US6051510A (en) * 1997-05-02 2000-04-18 Advanced Micro Devices, Inc. Method of using a hard mask to grow dielectrics with varying characteristics
US6037224A (en) * 1997-05-02 2000-03-14 Advanced Micro Devices, Inc. Method for growing dual oxide thickness using nitrided oxides for oxidation suppression
US6555484B1 (en) * 1997-06-19 2003-04-29 Cypress Semiconductor Corp. Method for controlling the oxidation of implanted silicon
US6100149A (en) * 1997-07-01 2000-08-08 Steag Rtp Systems Method for rapid thermal processing (RTP) of silicon substrates
US5935650A (en) * 1997-10-17 1999-08-10 Lerch; Wilfried Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system
US5918133A (en) * 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US6146934A (en) * 1997-12-19 2000-11-14 Advanced Micro Devices, Inc. Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
US6077751A (en) * 1998-01-29 2000-06-20 Steag Rtp Systems Gmbh Method of rapid thermal processing (RTP) of ion implanted silicon
US6221789B1 (en) * 1998-07-29 2001-04-24 Intel Corporation Thin oxides of silicon
US6235590B1 (en) 1998-12-18 2001-05-22 Lsi Logic Corporation Fabrication of differential gate oxide thicknesses on a single integrated circuit chip
KR100455737B1 (ko) 1998-12-30 2005-04-19 주식회사 하이닉스반도체 반도체소자의게이트산화막형성방법
JP2000232222A (ja) 1999-02-10 2000-08-22 Nec Corp 半導体装置の製造方法
US6110780A (en) * 1999-04-01 2000-08-29 Taiwan Semiconductor Manufacturing Company Using NO or N2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory
US6380033B1 (en) * 1999-09-20 2002-04-30 Advanced Micro Devices, Inc. Process to improve read disturb for NAND flash memory devices
US6284602B1 (en) * 1999-09-20 2001-09-04 Advanced Micro Devices, Inc. Process to reduce post cycling program VT dispersion for NAND flash memory devices
US6407008B1 (en) 2000-05-05 2002-06-18 Integrated Device Technology, Inc. Method of forming an oxide layer
US6339001B1 (en) 2000-06-16 2002-01-15 International Business Machines Corporation Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist
US6261972B1 (en) * 2000-11-06 2001-07-17 Infineon Technologies Ag Dual gate oxide process for uniform oxide thickness
JP2003168796A (ja) * 2001-11-30 2003-06-13 Sanyo Electric Co Ltd 半導体装置の製造方法
US6635584B2 (en) * 2001-12-28 2003-10-21 Texas Instruments Incorporated Versatile system for forming uniform wafer surfaces
US6821868B2 (en) * 2002-12-27 2004-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming nitrogen enriched gate dielectric with low effective oxide thickness
KR101144218B1 (ko) * 2004-05-06 2012-05-10 싸이던스 코포레이션 분리 채널 안티퓨즈 어레이 구조
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
US7879694B1 (en) 2004-07-13 2011-02-01 National Semiconductor Corporation System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process
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US20110147817A1 (en) * 2009-12-17 2011-06-23 Infineon Technologies Austria Ag Semiconductor component having an oxide layer

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Also Published As

Publication number Publication date
EP0696051B1 (de) 1999-12-15
EP0696051A1 (de) 1996-02-07
JP2008028403A (ja) 2008-02-07
ATE187844T1 (de) 2000-01-15
DE69513899D1 (de) 2000-01-20
US5498577A (en) 1996-03-12
JPH08172138A (ja) 1996-07-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HOESSLE PATENTANWAELTE PARTNERSCHAFT, 70173 STUTTG

8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY