DE69502350D1 - SOI (Silizium auf Isolator)-Logikschaltung mit niedriger Spannung - Google Patents

SOI (Silizium auf Isolator)-Logikschaltung mit niedriger Spannung

Info

Publication number
DE69502350D1
DE69502350D1 DE69502350T DE69502350T DE69502350D1 DE 69502350 D1 DE69502350 D1 DE 69502350D1 DE 69502350 T DE69502350 T DE 69502350T DE 69502350 T DE69502350 T DE 69502350T DE 69502350 D1 DE69502350 D1 DE 69502350D1
Authority
DE
Germany
Prior art keywords
insulator
silicon
low voltage
logic circuit
voltage soi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69502350T
Other languages
English (en)
Other versions
DE69502350T2 (de
Inventor
Takakuni Douseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Application granted granted Critical
Publication of DE69502350D1 publication Critical patent/DE69502350D1/de
Publication of DE69502350T2 publication Critical patent/DE69502350T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
DE69502350T 1994-06-28 1995-06-27 SOI (Silizium auf Isolator)-Logikschaltung mit niedriger Spannung Expired - Lifetime DE69502350T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP16885194 1994-06-28
JP33464094 1994-12-20

Publications (2)

Publication Number Publication Date
DE69502350D1 true DE69502350D1 (de) 1998-06-10
DE69502350T2 DE69502350T2 (de) 1998-10-29

Family

ID=26492395

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69502350T Expired - Lifetime DE69502350T2 (de) 1994-06-28 1995-06-27 SOI (Silizium auf Isolator)-Logikschaltung mit niedriger Spannung

Country Status (3)

Country Link
US (1) US5594371A (de)
EP (1) EP0690510B1 (de)
DE (1) DE69502350T2 (de)

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JP4736313B2 (ja) * 2002-09-10 2011-07-27 日本電気株式会社 薄膜半導体装置
US7334198B2 (en) * 2002-12-31 2008-02-19 Transmeta Corporation Software controlled transistor body bias
JP4435553B2 (ja) * 2003-12-12 2010-03-17 パナソニック株式会社 半導体装置
KR100585886B1 (ko) * 2004-01-27 2006-06-01 삼성전자주식회사 동적 문턱 전압을 가지는 반도체 회로
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US7164291B2 (en) * 2004-08-11 2007-01-16 Texas Instruments Incorporated Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors
JP4261507B2 (ja) * 2005-03-31 2009-04-30 富士通マイクロエレクトロニクス株式会社 クロックネットワークの消費電力低減回路
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US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
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JP6340310B2 (ja) * 2014-12-17 2018-06-06 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびウェラブル装置
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
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US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
JP6921780B2 (ja) 2018-04-13 2021-08-18 ルネサスエレクトロニクス株式会社 半導体装置
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Also Published As

Publication number Publication date
US5594371A (en) 1997-01-14
DE69502350T2 (de) 1998-10-29
EP0690510A1 (de) 1996-01-03
EP0690510B1 (de) 1998-05-06

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