DE69427554T2 - Verfahren zur Herstellung von Widerständen für integrierte Schaltkreise unter Verwendung von Gräben - Google Patents

Verfahren zur Herstellung von Widerständen für integrierte Schaltkreise unter Verwendung von Gräben

Info

Publication number
DE69427554T2
DE69427554T2 DE69427554T DE69427554T DE69427554T2 DE 69427554 T2 DE69427554 T2 DE 69427554T2 DE 69427554 T DE69427554 T DE 69427554T DE 69427554 T DE69427554 T DE 69427554T DE 69427554 T2 DE69427554 T2 DE 69427554T2
Authority
DE
Germany
Prior art keywords
trenches
integrated circuits
manufacturing resistors
resistors
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69427554T
Other languages
English (en)
Other versions
DE69427554D1 (de
Inventor
John M Boyd
Joseph P Ellul
Sing P Tay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Nortel Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nortel Networks Ltd filed Critical Nortel Networks Ltd
Application granted granted Critical
Publication of DE69427554D1 publication Critical patent/DE69427554D1/de
Publication of DE69427554T2 publication Critical patent/DE69427554T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69427554T 1993-03-24 1994-03-08 Verfahren zur Herstellung von Widerständen für integrierte Schaltkreise unter Verwendung von Gräben Expired - Fee Related DE69427554T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002092370A CA2092370C (en) 1993-03-24 1993-03-24 Forming resistors for integrated circuits

Publications (2)

Publication Number Publication Date
DE69427554D1 DE69427554D1 (de) 2001-08-02
DE69427554T2 true DE69427554T2 (de) 2001-10-04

Family

ID=4151343

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427554T Expired - Fee Related DE69427554T2 (de) 1993-03-24 1994-03-08 Verfahren zur Herstellung von Widerständen für integrierte Schaltkreise unter Verwendung von Gräben

Country Status (5)

Country Link
EP (1) EP0621631B1 (de)
JP (1) JP3739814B2 (de)
KR (1) KR100313412B1 (de)
CA (1) CA2092370C (de)
DE (1) DE69427554T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4667821B2 (ja) * 2004-10-13 2011-04-13 シャープ株式会社 半導体装置
KR100699833B1 (ko) 2005-01-22 2007-03-27 삼성전자주식회사 균일한 저항값을 가진 저항소자 및 이를 이용한 반도체 소자
KR100672160B1 (ko) * 2005-12-28 2007-01-19 주식회사 하이닉스반도체 플래쉬 메모리 소자의 레지스터 형성방법
JP5138274B2 (ja) 2007-05-25 2013-02-06 三菱電機株式会社 半導体装置
EP2286442B1 (de) * 2008-05-13 2016-07-27 Ipdia Verfahren zur herstellung von niederwertigen widerständen in einem halbleitermaterial
JP5563811B2 (ja) * 2009-12-09 2014-07-30 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US10083781B2 (en) 2015-10-30 2018-09-25 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10438729B2 (en) 2017-11-10 2019-10-08 Vishay Dale Electronics, Llc Resistor with upper surface heat dissipation
JP7157027B2 (ja) 2019-09-12 2022-10-19 株式会社東芝 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0719838B2 (ja) * 1985-07-19 1995-03-06 松下電器産業株式会社 半導体装置およびその製造方法
JPH01144648A (ja) * 1987-11-30 1989-06-06 Fujitsu Ltd 半導体装置
JPH01295440A (ja) * 1988-05-24 1989-11-29 Nissan Motor Co Ltd 半導体装置
EP0391123A3 (de) * 1989-04-04 1991-09-11 Texas Instruments Incorporated Trench-Widerstand und -Kondensator mit vergrösserter Länge
JPH0575026A (ja) * 1991-09-12 1993-03-26 Matsushita Electron Corp 抵抗素子の製造方法

Also Published As

Publication number Publication date
CA2092370A1 (en) 1994-09-25
CA2092370C (en) 1997-03-18
DE69427554D1 (de) 2001-08-02
JPH06302766A (ja) 1994-10-28
KR100313412B1 (ko) 2002-04-06
KR940022595A (ko) 1994-10-21
JP3739814B2 (ja) 2006-01-25
EP0621631B1 (de) 2001-06-27
EP0621631A1 (de) 1994-10-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee