DE69427532D1 - Verfahren zur reduzierung den abstandes zwischen den horizontalen benachbarten schwebenden gates einer flash eprom anordnung - Google Patents

Verfahren zur reduzierung den abstandes zwischen den horizontalen benachbarten schwebenden gates einer flash eprom anordnung

Info

Publication number
DE69427532D1
DE69427532D1 DE69427532T DE69427532T DE69427532D1 DE 69427532 D1 DE69427532 D1 DE 69427532D1 DE 69427532 T DE69427532 T DE 69427532T DE 69427532 T DE69427532 T DE 69427532T DE 69427532 D1 DE69427532 D1 DE 69427532D1
Authority
DE
Germany
Prior art keywords
reducing
distance
floating gates
flash eprom
next floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69427532T
Other languages
English (en)
Other versions
DE69427532T2 (de
Inventor
Albert Bergemont
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69427532D1 publication Critical patent/DE69427532D1/de
Publication of DE69427532T2 publication Critical patent/DE69427532T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69427532T 1994-02-17 1994-10-12 Verfahren zur reduzierung den abstandes zwischen den horizontalen benachbarten schwebenden gates einer flash eprom anordnung Expired - Lifetime DE69427532T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19773794A 1994-02-17 1994-02-17
PCT/US1994/011589 WO1995022837A1 (en) 1994-02-17 1994-10-12 A method for reducing the spacing between the horizontally-adjacent floating gates of a flash eprom array

Publications (2)

Publication Number Publication Date
DE69427532D1 true DE69427532D1 (de) 2001-07-26
DE69427532T2 DE69427532T2 (de) 2002-04-18

Family

ID=22730559

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427532T Expired - Lifetime DE69427532T2 (de) 1994-02-17 1994-10-12 Verfahren zur reduzierung den abstandes zwischen den horizontalen benachbarten schwebenden gates einer flash eprom anordnung

Country Status (4)

Country Link
US (2) US5566106A (de)
EP (1) EP0694211B1 (de)
DE (1) DE69427532T2 (de)
WO (1) WO1995022837A1 (de)

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US5834161A (en) * 1995-09-18 1998-11-10 Hyundai Electronics Industries Co., Ltd. Method for fabricating word lines of a semiconductor device
US5659500A (en) * 1995-09-26 1997-08-19 Texas Instruments Incorporated Nonvolatile memory array with compatible vertical source lines
US5658814A (en) * 1996-07-09 1997-08-19 Micron Technology, Inc. Method of forming a line of high density floating gate transistors
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6093650A (en) * 1997-12-17 2000-07-25 Advanced Micro Devices, Inc. Method for fully planarized conductive line for a stack gate
FR2778018B1 (fr) * 1998-04-28 2000-06-23 Sgs Thomson Microelectronics Procede de fabrication de dispositifs eeprom
TW390028B (en) * 1998-06-08 2000-05-11 United Microelectronics Corp A flash memory structure and its manufacturing
KR100316714B1 (ko) * 1998-07-11 2001-12-12 윤종용 플래쉬 메모리소자의 셀 제조방법
US6153469A (en) * 1998-07-13 2000-11-28 Samsung Electronics, Co., Ltd. Method of fabricating cell of flash memory device
KR100314127B1 (ko) * 1999-04-22 2001-11-17 윤종용 반도체소자의 부유게이트 형성방법
US6225162B1 (en) * 1999-07-06 2001-05-01 Taiwan Semiconductor Manufacturing Company Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application
US6750978B1 (en) * 2000-04-27 2004-06-15 Leapfrog Enterprises, Inc. Print media information system with a portable print media receiving unit assembly
JP2002064157A (ja) * 2000-06-09 2002-02-28 Toshiba Corp 半導体メモリ集積回路及びその製造方法
US6403494B1 (en) 2000-08-14 2002-06-11 Taiwan Semiconductor Manufacturing Company Method of forming a floating gate self-aligned to STI on EEPROM
KR100355238B1 (ko) * 2000-10-27 2002-10-11 삼성전자 주식회사 플레쉬 메모리 소자의 셀 제조 방법
US6627524B2 (en) * 2001-06-06 2003-09-30 Micron Technology, Inc. Methods of forming transistor gates; and methods of forming programmable read-only memory constructions
US6954199B2 (en) 2001-06-18 2005-10-11 Leapfrog Enterprises, Inc. Three dimensional interactive system
US6762092B2 (en) * 2001-08-08 2004-07-13 Sandisk Corporation Scalable self-aligned dual floating gate memory cell array and methods of forming the array
US6462372B1 (en) 2001-10-09 2002-10-08 Silicon-Based Technology Corp. Scaled stack-gate flash memory device
KR20040091016A (ko) * 2002-02-06 2004-10-27 리이프프로그 엔터프라이시스, 인코포레이티드 인터랙티브 장치 및 방법
US6894930B2 (en) 2002-06-19 2005-05-17 Sandisk Corporation Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
US6756619B2 (en) * 2002-08-26 2004-06-29 Micron Technology, Inc. Semiconductor constructions
ITMI20022784A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
ITMI20022785A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
JP2006513576A (ja) * 2003-01-22 2006-04-20 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 改良された浮遊ゲート絶縁と浮遊ゲートの製造方法
US7078349B2 (en) * 2003-07-31 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method to form self-aligned floating gate to diffusion structures in flash
KR100780866B1 (ko) * 2006-12-14 2007-11-30 삼성전자주식회사 비휘발성 메모리 소자 및 그 형성방법
US7745285B2 (en) 2007-03-30 2010-06-29 Sandisk Corporation Methods of forming and operating NAND memory with side-tunneling
US8367460B2 (en) 2010-06-22 2013-02-05 Micron Technology, Inc. Horizontally oriented and vertically stacked memory cells

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US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
JPS639152A (ja) * 1986-06-30 1988-01-14 Toshiba Corp 半導体装置の製造方法
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
FR2634318B1 (fr) * 1988-07-13 1992-02-21 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire integree
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US5070032A (en) * 1989-03-15 1991-12-03 Sundisk Corporation Method of making dense flash eeprom semiconductor memory structures
IT1236980B (it) * 1989-12-22 1993-05-12 Sgs Thomson Microelectronics Cella di memoria eprom non volatile a gate divisa e processo ad isolamento di campo autoallineato per l'ottenimento della cella suddetta
KR970000533B1 (ko) * 1990-12-20 1997-01-13 후지쓰 가부시끼가이샤 Eprom 및 그 제조방법
US5268320A (en) * 1990-12-26 1993-12-07 Intel Corporation Method of increasing the accuracy of an analog circuit employing floating gate memory devices
US5212541A (en) * 1991-04-18 1993-05-18 National Semiconductor Corporation Contactless, 5v, high speed eprom/flash eprom array utilizing cells programmed using source side injection
US5120670A (en) * 1991-04-18 1992-06-09 National Semiconductor Corporation Thermal process for implementing the planarization inherent to stacked etch in virtual ground EPROM memories
JP3043135B2 (ja) * 1991-09-26 2000-05-22 新日本製鐵株式会社 不揮発性半導体メモリの製造方法
US5284784A (en) * 1991-10-02 1994-02-08 National Semiconductor Corporation Buried bit-line source-side injection flash memory cell
JPH05121701A (ja) * 1991-10-25 1993-05-18 Rohm Co Ltd Ｎａｎｄ構造の半導体装置の製造方法
US5296410A (en) * 1992-12-16 1994-03-22 Samsung Electronics Co., Ltd. Method for separating fine patterns of a semiconductor device

Also Published As

Publication number Publication date
DE69427532T2 (de) 2002-04-18
WO1995022837A1 (en) 1995-08-24
EP0694211B1 (de) 2001-06-20
EP0694211A1 (de) 1996-01-31
US5688705A (en) 1997-11-18
US5566106A (en) 1996-10-15

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