DE69427421D1 - Speichersteuereinheit mit hohem Grade der Gleichzeitigkeit und Arbeitsteilung - Google Patents

Speichersteuereinheit mit hohem Grade der Gleichzeitigkeit und Arbeitsteilung

Info

Publication number
DE69427421D1
DE69427421D1 DE69427421T DE69427421T DE69427421D1 DE 69427421 D1 DE69427421 D1 DE 69427421D1 DE 69427421 T DE69427421 T DE 69427421T DE 69427421 T DE69427421 T DE 69427421T DE 69427421 D1 DE69427421 D1 DE 69427421D1
Authority
DE
Germany
Prior art keywords
memory
responsible
state machine
cycle
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69427421T
Other languages
English (en)
Other versions
DE69427421T2 (de
Inventor
John A Landry
Paul A Santeler
Gary W Thome
Randy M Bonella
Michael J Collins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69427421D1 publication Critical patent/DE69427421D1/de
Publication of DE69427421T2 publication Critical patent/DE69427421T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
DE69427421T 1993-03-22 1994-03-22 Speichersteuereinheit mit hohem Grade der Gleichzeitigkeit und Arbeitsteilung Expired - Lifetime DE69427421T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/034,290 US5537555A (en) 1993-03-22 1993-03-22 Fully pipelined and highly concurrent memory controller

Publications (2)

Publication Number Publication Date
DE69427421D1 true DE69427421D1 (de) 2001-07-19
DE69427421T2 DE69427421T2 (de) 2001-11-15

Family

ID=21875479

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427421T Expired - Lifetime DE69427421T2 (de) 1993-03-22 1994-03-22 Speichersteuereinheit mit hohem Grade der Gleichzeitigkeit und Arbeitsteilung

Country Status (6)

Country Link
US (1) US5537555A (de)
EP (1) EP0617365B1 (de)
JP (1) JP2597954B2 (de)
AT (1) ATE202227T1 (de)
CA (1) CA2119174C (de)
DE (1) DE69427421T2 (de)

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Also Published As

Publication number Publication date
EP0617365B1 (de) 2001-06-13
JP2597954B2 (ja) 1997-04-09
ATE202227T1 (de) 2001-06-15
CA2119174A1 (en) 1994-09-23
JPH076084A (ja) 1995-01-10
CA2119174C (en) 1998-10-20
DE69427421T2 (de) 2001-11-15
EP0617365A1 (de) 1994-09-28
US5537555A (en) 1996-07-16

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