DE69426713D1 - Integrierte Logikschaltung mit Logikgattern mit einem einzigen Eingang - Google Patents

Integrierte Logikschaltung mit Logikgattern mit einem einzigen Eingang

Info

Publication number
DE69426713D1
DE69426713D1 DE69426713T DE69426713T DE69426713D1 DE 69426713 D1 DE69426713 D1 DE 69426713D1 DE 69426713 T DE69426713 T DE 69426713T DE 69426713 T DE69426713 T DE 69426713T DE 69426713 D1 DE69426713 D1 DE 69426713D1
Authority
DE
Germany
Prior art keywords
single input
logic circuit
integrated
logic
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69426713T
Other languages
English (en)
Other versions
DE69426713T2 (de
Inventor
Robert Blauschild
Daniel Linebarger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69426713D1 publication Critical patent/DE69426713D1/de
Publication of DE69426713T2 publication Critical patent/DE69426713T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE69426713T 1993-06-16 1994-06-09 Integrierte Logikschaltung mit Logikgattern mit einem einzigen Eingang Expired - Fee Related DE69426713T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US7871993A 1993-06-16 1993-06-16

Publications (2)

Publication Number Publication Date
DE69426713D1 true DE69426713D1 (de) 2001-03-29
DE69426713T2 DE69426713T2 (de) 2001-09-06

Family

ID=22145818

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69426713T Expired - Fee Related DE69426713T2 (de) 1993-06-16 1994-06-09 Integrierte Logikschaltung mit Logikgattern mit einem einzigen Eingang

Country Status (5)

Country Link
US (1) US5610539A (de)
EP (1) EP0630113B1 (de)
JP (1) JP3530582B2 (de)
KR (1) KR100332847B1 (de)
DE (1) DE69426713T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3507621B2 (ja) * 1996-05-28 2004-03-15 株式会社東芝 半導体集積回路
KR100275948B1 (ko) 1998-04-14 2000-12-15 김영환 차동모드낸드/노어게이트
US6137310A (en) * 1999-02-19 2000-10-24 Teradyne, Inc. Serial switch driver architecture for automatic test equipment
US6215330B1 (en) 1999-06-11 2001-04-10 Trw Inc. Differential diode transistor logic (DDTL) circuit enhancements
US6380794B1 (en) 2000-03-24 2002-04-30 Sige Microsystems Inc. Hybrid circuit having current source controlled by a comparator
KR100387920B1 (ko) * 2000-08-22 2003-06-18 김대진 도자기용 유약의 제조 및 도포방법
KR100387919B1 (ko) * 2000-08-22 2003-06-18 김대진 도자기용 유약의 제조 및 도포방법
US6489811B2 (en) * 2001-03-08 2002-12-03 Hiband Semiconductor, Inc. Logic gate with symmetrical propagation delay from any input to any output and a controlled output pulse width
US10256998B1 (en) * 2018-05-03 2019-04-09 Micron Technology, Inc. Reducing supply noise in current mode logic transmitters

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3509362A (en) * 1966-08-19 1970-04-28 Rca Corp Switching circuit
BE755245A (fr) 1969-08-25 1971-02-25 Siemens Ag Circuit de porte logique realise selon la technique des circuits logiques a emetteur couple (ecl)
JPS56123128A (en) * 1980-03-04 1981-09-28 Nec Corp Logic circuit
JPS56156026A (en) * 1980-05-02 1981-12-02 Hitachi Ltd Composite logical circuit
US4408134A (en) * 1981-01-19 1983-10-04 Advanced Micro Devices, Inc. Unitary exclusive or-and logic circuit
US4390848A (en) * 1981-02-12 1983-06-28 Signetics Linear transconductance amplifier
JPS5945706A (ja) * 1982-09-09 1984-03-14 Nippon Shiguneteitsukusu Kk 差動増幅回路
JPS5981921A (ja) * 1982-11-01 1984-05-11 Hitachi Ltd 高速論理回路
US4542305A (en) * 1983-02-22 1985-09-17 Signetics Corporation Impedance buffer with reduced settling time
US4754173A (en) * 1985-06-13 1988-06-28 Digital Equipment Corporation Emitter coupled logic latch with boolean logic input gating network
JPS62105528A (ja) * 1985-11-01 1987-05-16 Hitachi Ltd 動作マ−ジンを拡大させた高速論理回路
US4677315A (en) * 1986-07-28 1987-06-30 Signetics Corporation Switching circuit with hysteresis
US4792706A (en) * 1986-12-16 1988-12-20 Texas Instruments Incorporated ECL gates using diode-clamped loads and Schottky clamped reference bias
US4857771A (en) * 1986-12-16 1989-08-15 Texas Instruments Incorporated Method of making an ECL logic circuit having diode-clamped loads and reference bias
JPS63302621A (ja) * 1987-06-02 1988-12-09 Fujitsu Ltd 半導体集積回路
JP2824780B2 (ja) * 1989-04-18 1998-11-18 科学技術振興事業団 論理回路
US5111074A (en) * 1990-07-26 1992-05-05 Regents Of The University Of Minnesota Multi-input compound function complementary noise-immune logic
US5115206A (en) * 1990-11-08 1992-05-19 North American Philips Corp., Signetics Division Merged differential amplifier and current source
US5206547A (en) * 1992-01-06 1993-04-27 Motorola, Inc. High-speed programmable state counter

Also Published As

Publication number Publication date
JP3530582B2 (ja) 2004-05-24
KR100332847B1 (ko) 2002-11-13
DE69426713T2 (de) 2001-09-06
JPH0738414A (ja) 1995-02-07
US5610539A (en) 1997-03-11
EP0630113B1 (de) 2001-02-21
EP0630113A2 (de) 1994-12-21
EP0630113A3 (de) 1996-03-06
KR950002231A (ko) 1995-01-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee