DE69416619T2 - Halbleiterspeicheranordnung und Verfahren zur Herstellung - Google Patents

Halbleiterspeicheranordnung und Verfahren zur Herstellung

Info

Publication number
DE69416619T2
DE69416619T2 DE69416619T DE69416619T DE69416619T2 DE 69416619 T2 DE69416619 T2 DE 69416619T2 DE 69416619 T DE69416619 T DE 69416619T DE 69416619 T DE69416619 T DE 69416619T DE 69416619 T2 DE69416619 T2 DE 69416619T2
Authority
DE
Germany
Prior art keywords
region
semiconductor device
layer
barrier layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69416619T
Other languages
German (de)
English (en)
Other versions
DE69416619D1 (de
Inventor
Jun-Ichi Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tohoku University NUC
Original Assignee
Zaidan Hojin Handotai Kenkyu Shinkokai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zaidan Hojin Handotai Kenkyu Shinkokai filed Critical Zaidan Hojin Handotai Kenkyu Shinkokai
Publication of DE69416619D1 publication Critical patent/DE69416619D1/de
Application granted granted Critical
Publication of DE69416619T2 publication Critical patent/DE69416619T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/021Manufacture or treatment of gated diodes, e.g. field-controlled diodes [FCD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/01Manufacture or treatment
    • H10D48/021Manufacture or treatment of two-electrode devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/812Charge-trapping diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Landscapes

  • Semiconductor Memories (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Non-Volatile Memory (AREA)
DE69416619T 1993-05-12 1994-05-10 Halbleiterspeicheranordnung und Verfahren zur Herstellung Expired - Fee Related DE69416619T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14712893 1993-05-12

Publications (2)

Publication Number Publication Date
DE69416619D1 DE69416619D1 (de) 1999-04-01
DE69416619T2 true DE69416619T2 (de) 1999-09-30

Family

ID=15423194

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69416619T Expired - Fee Related DE69416619T2 (de) 1993-05-12 1994-05-10 Halbleiterspeicheranordnung und Verfahren zur Herstellung

Country Status (5)

Country Link
US (1) US5485017A (OSRAM)
EP (1) EP0631326B1 (OSRAM)
KR (1) KR0157662B1 (OSRAM)
DE (1) DE69416619T2 (OSRAM)
TW (1) TW241381B (OSRAM)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665978A (en) * 1995-05-25 1997-09-09 Matsushita Electric Industrial Co., Ltd. Nonlinear element and bistable memory device
JP3397516B2 (ja) * 1995-06-08 2003-04-14 三菱電機株式会社 半導体記憶装置及び半導体集積回路装置
EP0843360A1 (en) * 1996-11-15 1998-05-20 Hitachi Europe Limited Memory device
JP3853905B2 (ja) * 1997-03-18 2006-12-06 株式会社東芝 量子効果装置とblトンネル素子を用いた装置
US6421682B1 (en) 1999-07-26 2002-07-16 Microsoft Corporation Catalog management system architecture having data table objects and logic table objects
JP5533661B2 (ja) * 2008-10-29 2014-06-25 富士通株式会社 化合物半導体装置及びその製造方法
US10103226B2 (en) 2012-04-30 2018-10-16 International Business Machines Corporation Method of fabricating tunnel transistors with abrupt junctions
US9508854B2 (en) 2013-12-06 2016-11-29 Ecole Polytechnique Federale De Lausanne (Epfl) Single field effect transistor capacitor-less memory device and method of operating the same
DE102016015475B3 (de) * 2016-12-28 2018-01-11 3-5 Power Electronics GmbH IGBT Halbleiterstruktur
KR20180129457A (ko) * 2017-05-26 2018-12-05 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972059A (en) * 1973-12-28 1976-07-27 International Business Machines Corporation Dielectric diode, fabrication thereof, and charge store memory therewith
JPS5591166A (en) * 1978-12-28 1980-07-10 Nippon Gakki Seizo Kk Semiconductor memory
JPS56124273A (en) * 1980-03-04 1981-09-29 Semiconductor Res Found Semiconductor device
JPS5940576A (ja) * 1982-08-30 1984-03-06 Junichi Nishizawa フオトサイリスタ
JPS60254777A (ja) * 1984-05-31 1985-12-16 Fujitsu Ltd 半導体装置
JPS61158184A (ja) * 1984-12-29 1986-07-17 Fujitsu Ltd 半導体装置
US5216262A (en) * 1992-03-02 1993-06-01 Raphael Tsu Quantum well structures useful for semiconductor devices

Also Published As

Publication number Publication date
EP0631326B1 (en) 1999-02-24
KR0157662B1 (ko) 1998-10-15
KR940027148A (ko) 1994-12-10
EP0631326A2 (en) 1994-12-28
DE69416619D1 (de) 1999-04-01
TW241381B (OSRAM) 1995-02-21
US5485017A (en) 1996-01-16
EP0631326A3 (en) 1995-05-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: TOHOKU UNIVERSITY, SENDAI, MIYAGI, JP

8339 Ceased/non-payment of the annual fee