DE69323476T2 - Verfahren zur Herstellung eines selbstausrichtenden statischen Induktionsthyristors - Google Patents

Verfahren zur Herstellung eines selbstausrichtenden statischen Induktionsthyristors

Info

Publication number
DE69323476T2
DE69323476T2 DE69323476T DE69323476T DE69323476T2 DE 69323476 T2 DE69323476 T2 DE 69323476T2 DE 69323476 T DE69323476 T DE 69323476T DE 69323476 T DE69323476 T DE 69323476T DE 69323476 T2 DE69323476 T2 DE 69323476T2
Authority
DE
Germany
Prior art keywords
layer
forming
transistor
trenches
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69323476T
Other languages
German (de)
English (en)
Other versions
DE69323476D1 (de
Inventor
Maw-Rong Chin
Joseph E. Farb
Kuan Y. Liao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Application granted granted Critical
Publication of DE69323476D1 publication Critical patent/DE69323476D1/de
Publication of DE69323476T2 publication Critical patent/DE69323476T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/012—Manufacture or treatment of static induction transistors [SIT], e.g. permeable base transistors [PBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H10P14/416—
    • H10P50/00—
    • H10P76/204—

Landscapes

  • Junction Field-Effect Transistors (AREA)
DE69323476T 1992-11-24 1993-06-14 Verfahren zur Herstellung eines selbstausrichtenden statischen Induktionsthyristors Expired - Fee Related DE69323476T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/981,032 US5260227A (en) 1992-11-24 1992-11-24 Method of making a self aligned static induction transistor

Publications (2)

Publication Number Publication Date
DE69323476D1 DE69323476D1 (de) 1999-03-25
DE69323476T2 true DE69323476T2 (de) 1999-09-02

Family

ID=25528048

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69323476T Expired - Fee Related DE69323476T2 (de) 1992-11-24 1993-06-14 Verfahren zur Herstellung eines selbstausrichtenden statischen Induktionsthyristors

Country Status (6)

Country Link
US (1) US5260227A (en:Method)
EP (1) EP0600149B1 (en:Method)
JP (1) JPH077158A (en:Method)
KR (1) KR970004845B1 (en:Method)
DE (1) DE69323476T2 (en:Method)
TW (1) TW280009B (en:Method)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283201A (en) * 1988-05-17 1994-02-01 Advanced Power Technology, Inc. High density power device fabrication process
EP0732734B1 (en) * 1995-03-13 2003-05-14 Raytheon Company Method of making a self-aligned static induction transistor
US5807773A (en) * 1996-07-30 1998-09-15 Northrop Grumman Corporation Self-aligned gate fabrication process for silicon carbide static induction transistors
US5702987A (en) * 1996-08-26 1997-12-30 Chartered Semiconductor Manufacturing Pte Ltd Method of manufacture of self-aligned JFET
US6855970B2 (en) 2002-03-25 2005-02-15 Kabushiki Kaisha Toshiba High-breakdown-voltage semiconductor device
JP4623956B2 (ja) * 2003-11-12 2011-02-02 株式会社豊田中央研究所 Ｉｇｂｔ
US7187021B2 (en) * 2003-12-10 2007-03-06 General Electric Company Static induction transistor
US7750447B2 (en) * 2007-06-11 2010-07-06 Alpha & Omega Semiconductor, Ltd High voltage and high power boost converter with co-packaged Schottky diode
US8008897B2 (en) * 2007-06-11 2011-08-30 Alpha & Omega Semiconductor, Ltd Boost converter with integrated high power discrete FET and low voltage controller
US8021563B2 (en) * 2007-03-23 2011-09-20 Alpha & Omega Semiconductor, Ltd Etch depth determination for SGT technology
US7521332B2 (en) * 2007-03-23 2009-04-21 Alpha & Omega Semiconductor, Ltd Resistance-based etch depth determination for SGT technology
US8456141B2 (en) 2007-06-11 2013-06-04 Alpha & Omega Semiconductor, Inc. Boost converter with integrated high power discrete FET and low voltage controller

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2507821A1 (fr) * 1981-06-16 1982-12-17 Thomson Csf Transistor a effet de champ vertical a jonction et procede de fabrication
US4543706A (en) * 1984-02-24 1985-10-01 Gte Laboratories Incorporated Fabrication of junction field effect transistor with filled grooves
US4566172A (en) * 1984-02-24 1986-01-28 Gte Laboratories Incorporated Method of fabricating a static induction type recessed junction field effect transistor
US4611384A (en) * 1985-04-30 1986-09-16 Gte Laboratories Incorporated Method of making junction field effect transistor of static induction type
US4713358A (en) * 1986-05-02 1987-12-15 Gte Laboratories Incorporated Method of fabricating recessed gate static induction transistors
US5082795A (en) * 1986-12-05 1992-01-21 General Electric Company Method of fabricating a field effect semiconductor device having a self-aligned structure
US5164325A (en) * 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
JPH02143564A (ja) * 1988-11-25 1990-06-01 Matsushita Electric Works Ltd 静電誘導サイリスタの製造方法
JPH0817241B2 (ja) * 1989-01-18 1996-02-21 日本電気株式会社 細線電界効果トランジスタ及びその製造方法
US5143859A (en) * 1989-01-18 1992-09-01 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a static induction type switching device
US5169795A (en) * 1989-02-28 1992-12-08 Small Power Communication Systems Research Laboratories Co., Ltd. Method of manufacturing step cut type insulated gate SIT having low-resistance electrode

Also Published As

Publication number Publication date
KR950002064A (ko) 1995-01-04
US5260227A (en) 1993-11-09
EP0600149B1 (en) 1999-02-10
JPH077158A (ja) 1995-01-10
DE69323476D1 (de) 1999-03-25
KR970004845B1 (ko) 1997-04-04
EP0600149A3 (en) 1995-11-29
EP0600149A2 (en) 1994-06-08
TW280009B (en:Method) 1996-07-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee