DE69321149T2 - Halbleiter-Kontaktöffnungsstruktur und -verfahren - Google Patents

Halbleiter-Kontaktöffnungsstruktur und -verfahren

Info

Publication number
DE69321149T2
DE69321149T2 DE69321149T DE69321149T DE69321149T2 DE 69321149 T2 DE69321149 T2 DE 69321149T2 DE 69321149 T DE69321149 T DE 69321149T DE 69321149 T DE69321149 T DE 69321149T DE 69321149 T2 DE69321149 T2 DE 69321149T2
Authority
DE
Germany
Prior art keywords
contact opening
opening structure
semiconductor contact
semiconductor
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69321149T
Other languages
English (en)
Other versions
DE69321149D1 (de
Inventor
Lin Yih Shung
Lu Lun Tseng
Liou Fu Tai
Wei Che Chia
John Leonard Walters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69321149D1 publication Critical patent/DE69321149D1/de
Publication of DE69321149T2 publication Critical patent/DE69321149T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69321149T 1992-02-06 1993-01-29 Halbleiter-Kontaktöffnungsstruktur und -verfahren Expired - Fee Related DE69321149T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/832,088 US5246883A (en) 1992-02-06 1992-02-06 Semiconductor contact via structure and method

Publications (2)

Publication Number Publication Date
DE69321149D1 DE69321149D1 (de) 1998-10-29
DE69321149T2 true DE69321149T2 (de) 1999-02-18

Family

ID=25260653

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69321149T Expired - Fee Related DE69321149T2 (de) 1992-02-06 1993-01-29 Halbleiter-Kontaktöffnungsstruktur und -verfahren

Country Status (4)

Country Link
US (2) US5246883A (de)
EP (1) EP0555032B1 (de)
JP (1) JPH0645464A (de)
DE (1) DE69321149T2 (de)

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KR960004079B1 (en) * 1992-12-19 1996-03-26 Lg Semicon Co Ltd Contact hole forming method
TW230266B (de) * 1993-01-26 1994-09-11 American Telephone & Telegraph
JPH08511659A (ja) * 1994-04-07 1996-12-03 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 半導体本体表面に多層配線構造が設けられた半導体装置の製造方法
US5565384A (en) * 1994-04-28 1996-10-15 Texas Instruments Inc Self-aligned via using low permittivity dielectric
US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
US6495470B2 (en) * 1994-11-18 2002-12-17 Intel Corporation Contact and via fabrication technologies
JPH08203998A (ja) * 1995-01-20 1996-08-09 Sony Corp 多層配線の形成方法
JP3369817B2 (ja) * 1995-06-23 2003-01-20 三菱電機株式会社 半導体装置
JP3703885B2 (ja) 1995-09-29 2005-10-05 株式会社東芝 半導体記憶装置とその製造方法
US6294799B1 (en) * 1995-11-27 2001-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
US5940732A (en) * 1995-11-27 1999-08-17 Semiconductor Energy Laboratory Co., Method of fabricating semiconductor device
US5849635A (en) * 1996-07-11 1998-12-15 Micron Technology, Inc. Semiconductor processing method of forming an insulating dielectric layer and a contact opening therein
US5883002A (en) * 1996-08-29 1999-03-16 Winbond Electronics Corp. Method of forming contact profile by improving TEOS/BPSG selectivity for manufacturing a semiconductor device
US5914801A (en) * 1996-09-27 1999-06-22 Mcnc Microelectromechanical devices including rotating plates and related methods
GB2325083B (en) * 1997-05-09 1999-04-14 United Microelectronics Corp A dual damascene process
JPH10270555A (ja) 1997-03-27 1998-10-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6271117B1 (en) * 1997-06-23 2001-08-07 Vanguard International Semiconductor Corporation Process for a nail shaped landing pad plug
JP3568385B2 (ja) * 1998-03-16 2004-09-22 沖電気工業株式会社 半導体装置の製造方法
JPH11307512A (ja) * 1998-04-23 1999-11-05 Sony Corp エッチング方法
US6492276B1 (en) 1998-05-29 2002-12-10 Taiwan Semiconductor Manufacturing Company Hard masking method for forming residue free oxygen containing plasma etched layer
US6019906A (en) * 1998-05-29 2000-02-01 Taiwan Semiconductor Manufacturing Company Hard masking method for forming patterned oxygen containing plasma etchable layer
US6007733A (en) * 1998-05-29 1999-12-28 Taiwan Semiconductor Manufacturing Company Hard masking method for forming oxygen containing plasma etchable layer
US6117791A (en) 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US7173339B1 (en) 1998-06-22 2007-02-06 Micron Technology, Inc. Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
US6875371B1 (en) 1998-06-22 2005-04-05 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6121098A (en) * 1998-06-30 2000-09-19 Infineon Technologies North America Corporation Semiconductor manufacturing method
JP2000077520A (ja) * 1998-08-28 2000-03-14 Fujitsu Ltd 半導体装置の製造方法
US6440859B1 (en) 1998-09-25 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for etching passivation layer of wafer
US6475836B1 (en) 1999-03-29 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7224063B2 (en) 2001-06-01 2007-05-29 International Business Machines Corporation Dual-damascene metallization interconnection
KR100539232B1 (ko) * 2003-03-15 2005-12-27 삼성전자주식회사 디램 메모리 셀 및 그 제조방법
US6959037B2 (en) * 2003-09-15 2005-10-25 Spirent Communications Of Rockville, Inc. System and method for locating and determining discontinuities and estimating loop loss in a communications medium using frequency domain correlation
WO2009033837A2 (en) * 2007-09-11 2009-03-19 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US7704869B2 (en) * 2007-09-11 2010-04-27 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US7723851B2 (en) * 2007-09-11 2010-05-25 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4299024A (en) * 1980-02-25 1981-11-10 Harris Corporation Fabrication of complementary bipolar transistors and CMOS devices with poly gates
US4372034B1 (en) * 1981-03-26 1998-07-21 Intel Corp Process for forming contact openings through oxide layers
US4476156A (en) * 1983-03-10 1984-10-09 The United States Of America As Represented By The United States Department Of Energy Low temperature process for obtaining thin glass films
JPS60198847A (ja) * 1984-03-23 1985-10-08 Nec Corp 半導体装置およびその製造方法
US4587138A (en) * 1984-11-09 1986-05-06 Intel Corporation MOS rear end processing
JPS61166031A (ja) * 1984-12-25 1986-07-26 Fujitsu Ltd 絶縁膜のエツチング方法
JPS621246A (ja) * 1985-06-26 1987-01-07 Nec Corp 半導体装置およびその製造方法
DE3684298D1 (de) * 1986-01-09 1992-04-16 Ibm Verfahren zur herstellung eines kontakts unter verwendung der erweichung zweier glasschichten.
JPS62166523A (ja) * 1986-01-20 1987-07-23 Fujitsu Ltd 半導体装置の製造方法
JPS63182839A (ja) * 1987-01-23 1988-07-28 Nec Corp 半導体装置
EP0282820A1 (de) * 1987-03-13 1988-09-21 Siemens Aktiengesellschaft Verfahren zum Erzeugen von Kontaktlöchern mit abgeschrägten Flanken in Zwischenoxidschichten
JPS63276246A (ja) * 1987-05-08 1988-11-14 Nec Corp 半導体装置
JPH01233724A (ja) * 1988-03-14 1989-09-19 Nec Corp 半導体装置の製造方法
KR910006093B1 (ko) * 1988-06-30 1991-08-12 삼성전자 주식회사 반도체 장치의 제조방법
US5068711A (en) * 1989-03-20 1991-11-26 Fujitsu Limited Semiconductor device having a planarized surface

Also Published As

Publication number Publication date
US5246883A (en) 1993-09-21
US5841195A (en) 1998-11-24
JPH0645464A (ja) 1994-02-18
EP0555032B1 (de) 1998-09-23
EP0555032A1 (de) 1993-08-11
DE69321149D1 (de) 1998-10-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee