DE69232136D1 - Basiszellen-architektur für maskenprogrammierbare gattermatrix - Google Patents

Basiszellen-architektur für maskenprogrammierbare gattermatrix

Info

Publication number
DE69232136D1
DE69232136D1 DE69232136T DE69232136T DE69232136D1 DE 69232136 D1 DE69232136 D1 DE 69232136D1 DE 69232136 T DE69232136 T DE 69232136T DE 69232136 T DE69232136 T DE 69232136T DE 69232136 D1 DE69232136 D1 DE 69232136D1
Authority
DE
Germany
Prior art keywords
programmable gate
basic cell
cell architecture
mask programmable
gate matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69232136T
Other languages
English (en)
Other versions
DE69232136T2 (de
Inventor
Gamal Abbas El
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Physical IP Inc
Original Assignee
Artisan Components Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Artisan Components Inc filed Critical Artisan Components Inc
Publication of DE69232136D1 publication Critical patent/DE69232136D1/de
Application granted granted Critical
Publication of DE69232136T2 publication Critical patent/DE69232136T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/996—Masterslice integrated circuits using combined field effect technology and bipolar technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69232136T 1991-06-18 1992-06-11 Basiszellen-architektur für maskenprogrammierbare gattermatrix Expired - Fee Related DE69232136T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/717,140 US5289021A (en) 1990-05-15 1991-06-18 Basic cell architecture for mask programmable gate array with 3 or more size transistors
PCT/US1992/005003 WO1992022924A1 (en) 1991-06-18 1992-06-11 Basic cell architecture for mask programmable gate array

Publications (2)

Publication Number Publication Date
DE69232136D1 true DE69232136D1 (de) 2001-11-22
DE69232136T2 DE69232136T2 (de) 2002-03-07

Family

ID=24880867

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69232136T Expired - Fee Related DE69232136T2 (de) 1991-06-18 1992-06-11 Basiszellen-architektur für maskenprogrammierbare gattermatrix

Country Status (7)

Country Link
US (1) US5289021A (de)
EP (1) EP0591342B1 (de)
JP (1) JPH06508480A (de)
AU (1) AU2238692A (de)
DE (1) DE69232136T2 (de)
SG (1) SG49705A1 (de)
WO (1) WO1992022924A1 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5217915A (en) * 1991-04-08 1993-06-08 Texas Instruments Incorporated Method of making gate array base cell
JP3266644B2 (ja) * 1991-04-08 2002-03-18 テキサス インスツルメンツ インコーポレイテツド ゲートアレイ装置
JPH05243532A (ja) * 1991-11-01 1993-09-21 Texas Instr Inc <Ti> 複数のｐチャンネルトランジスタを有するゲートアレイ基本セル
US5452245A (en) * 1993-09-07 1995-09-19 Motorola, Inc. Memory efficient gate array cell
US5391943A (en) * 1994-01-10 1995-02-21 Mahant-Shetti; Shivaling S. Gate array cell with predefined connection patterns
IL109491A (en) * 1994-05-01 1999-11-30 Quick Tech Ltd Customizable logic array device
US5591995A (en) * 1994-05-10 1997-01-07 Texas Instruments, Incorporated Base cell for BiCMOS and CMOS gate arrays
JP2747223B2 (ja) * 1994-06-27 1998-05-06 日本電気アイシーマイコンシステム株式会社 半導体集積回路
US5422581A (en) * 1994-08-17 1995-06-06 Texas Instruments Incorporated Gate array cell with predefined connection patterns
JP2912174B2 (ja) * 1994-12-27 1999-06-28 日本電気株式会社 ライブラリ群及びそれを用いた半導体集積回路
US5552721A (en) * 1995-06-05 1996-09-03 International Business Machines Corporation Method and system for enhanced drive in programmmable gate arrays
US5684412A (en) * 1995-08-18 1997-11-04 Chip Express (Israel) Ltd. Cell forming part of a customizable logic array
EP0762653A3 (de) * 1995-08-18 1998-03-18 Chip Express (Israel) Ltd. Zelle für ein kundenspezifisch anpassbares logisches Feld
US6097221A (en) 1995-12-11 2000-08-01 Kawasaki Steel Corporation Semiconductor integrated circuit capable of realizing logic functions
US5990502A (en) * 1995-12-29 1999-11-23 Lsi Logic Corporation High density gate array cell architecture with metallization routing tracks having a variable pitch
US5796128A (en) * 1996-07-25 1998-08-18 Translogic Technology, Inc. Gate array with fully wired multiplexer circuits
JP3152635B2 (ja) * 1996-09-09 2001-04-03 三洋電機株式会社 マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器
US6031982A (en) * 1996-11-15 2000-02-29 Samsung Electronics Co., Ltd. Layout design of integrated circuit, especially datapath circuitry, using function cells formed with fixed basic cell and configurable interconnect networks
US6051031A (en) * 1997-02-05 2000-04-18 Virage Logic Corporation Module-based logic architecture and design flow for VLSI implementation
US5780883A (en) * 1997-02-28 1998-07-14 Translogic Technology, Inc. Gate array architecture for multiplexer based circuits
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US6177709B1 (en) 1997-06-30 2001-01-23 Synopsys, Inc. Cell based array having compute/drive ratios of N:1
US6445049B1 (en) * 1997-06-30 2002-09-03 Artisan Components, Inc. Cell based array comprising logic, transfer and drive cells
JP4301462B2 (ja) 1997-09-29 2009-07-22 川崎マイクロエレクトロニクス株式会社 電界効果トランジスタ
US6974978B1 (en) * 1999-03-04 2005-12-13 Intel Corporation Gate array architecture
US6480032B1 (en) 1999-03-04 2002-11-12 Intel Corporation Gate array architecture
US7299459B1 (en) 2000-01-19 2007-11-20 Sabio Labs, Inc. Parser for signomial and geometric programs
US6617621B1 (en) 2000-06-06 2003-09-09 Virage Logic Corporation Gate array architecture using elevated metal levels for customization
US6294927B1 (en) * 2000-06-16 2001-09-25 Chip Express (Israel) Ltd Configurable cell for customizable logic array device
JP2002026296A (ja) * 2000-06-22 2002-01-25 Internatl Business Mach Corp <Ibm> 半導体集積回路装置
US7065727B2 (en) * 2001-04-25 2006-06-20 Barcelona Design, Inc. Optimal simultaneous design and floorplanning of integrated circuit
US6954921B2 (en) * 2002-03-05 2005-10-11 Barcelona Design, Inc. Method and apparatus for automatic analog/mixed signal system design using geometric programming
US20030191611A1 (en) * 2002-04-05 2003-10-09 Hershenson Maria Del Mar Behavioral circuit modeling for geometric programming
US6802050B2 (en) 2002-04-07 2004-10-05 Barcelona Design, Inc. Efficient layout strategy for automated design layout tools
US6789246B1 (en) * 2002-04-07 2004-09-07 Barcelona Design, Inc. Method and apparatus for automatic layout of circuit structures
US6909330B2 (en) 2002-04-07 2005-06-21 Barcelona Design, Inc. Automatic phase lock loop design using geometric programming
US7093205B2 (en) * 2002-04-10 2006-08-15 Barcelona Design, Inc. Method and apparatus for efficient semiconductor process evaluation
US6988258B2 (en) * 2002-12-09 2006-01-17 Altera Corporation Mask-programmable logic device with building block architecture
US7081772B1 (en) * 2004-06-04 2006-07-25 Altera Corporation Optimizing logic in non-reprogrammable logic devices
US7725858B2 (en) * 2007-06-27 2010-05-25 Intel Corporation Providing a moat capacitance
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
GB201119099D0 (en) 2011-11-04 2011-12-21 Univ York Field-programmable gate array
KR102448030B1 (ko) * 2017-09-21 2022-09-28 삼성디스플레이 주식회사 표시장치
US10707755B1 (en) 2019-01-25 2020-07-07 International Business Machines Corporation Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL176029C (nl) * 1973-02-01 1985-02-01 Philips Nv Geintegreerde logische schakeling met komplementaire transistoren.
US4069494A (en) * 1973-02-17 1978-01-17 Ferranti Limited Inverter circuit arrangements
JPS57148363A (en) * 1981-03-11 1982-09-13 Toshiba Corp Gate array
ZA824093B (en) * 1981-06-25 1983-04-27 Squibb & Sons Inc Male incontinence device
JPS5851536A (ja) * 1981-09-24 1983-03-26 Ricoh Co Ltd マスタスライスチツプ
JPS58122771A (ja) * 1982-01-14 1983-07-21 Nec Corp 半導体集積回路装置
JPS6017932A (ja) * 1983-07-09 1985-01-29 Fujitsu Ltd ゲ−ト・アレイ
EP0131463B1 (de) * 1983-07-09 1989-03-15 Fujitsu Limited "Master-slice"-Halbleiteranordnung
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
JP2564787B2 (ja) * 1983-12-23 1996-12-18 富士通株式会社 ゲートアレー大規模集積回路装置及びその製造方法
JPS6242614A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd 複合トランジスタ形インバ−タ
US4649294A (en) * 1986-01-13 1987-03-10 Motorola, Inc. BIMOS logic gate
JPH0650761B2 (ja) * 1986-08-12 1994-06-29 富士通株式会社 半導体装置
JPH07120727B2 (ja) * 1987-03-27 1995-12-20 株式会社東芝 ＢｉＭＯＳ論理回路
JPS63306641A (ja) * 1987-06-08 1988-12-14 Nec Corp 半導体集積回路
US4829200A (en) * 1987-10-13 1989-05-09 Delco Electronics Corporation Logic circuits utilizing a composite junction transistor-MOSFET device
JPH02177457A (ja) * 1988-12-28 1990-07-10 Hitachi Ltd 半導体装置
JP2632420B2 (ja) * 1989-02-23 1997-07-23 三菱電機株式会社 半導体集積回路
JPH02284468A (ja) * 1989-04-26 1990-11-21 Nec Corp ゲートアレイ型半導体集積回路
DE68925897T2 (de) * 1989-04-28 1996-10-02 Ibm Gate-Array-Zelle, bestehend aus FET's von verschiedener und optimierter Grösse
US5068548A (en) * 1990-05-15 1991-11-26 Siarc Bicmos logic circuit for basic applications
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
JPH0479145A (ja) * 1990-07-20 1992-03-12 Koito Mfg Co Ltd 放電ランプ装置
JPH0479143A (ja) * 1990-07-23 1992-03-12 Jeol Ltd 高周波誘導結合プラズマ質量分析装置

Also Published As

Publication number Publication date
AU2238692A (en) 1993-01-12
SG49705A1 (en) 1998-06-15
EP0591342B1 (de) 2001-10-17
EP0591342A4 (de) 1994-03-18
EP0591342A1 (de) 1994-04-13
JPH06508480A (ja) 1994-09-22
DE69232136T2 (de) 2002-03-07
US5289021A (en) 1994-02-22
WO1992022924A1 (en) 1992-12-23

Similar Documents

Publication Publication Date Title
DE69232136D1 (de) Basiszellen-architektur für maskenprogrammierbare gattermatrix
DE69228581D1 (de) Steuergerät für eine Matrix
EP0804617A4 (de) Bcl-x/bcl-2 assoreizte zelltodregulatoren
FI924787L (fi) Sackaridmatris
DE69430544D1 (de) Verbindungsmechanismus für strukturelemente
DE69327741D1 (de) Photopolymerisierbare Zusammensetzung
NO933344D0 (no) Sluseventil
NO930824D0 (no) Lukkemekanisme
NO921395D0 (no) Nedstengingsventil for foringsroer
FI934969L (fi) Kyvettmatris
IT8467141A0 (it) Valvola a saracinesca
DE69423077D1 (de) Steuerungsvorrichtungen für nichtflüchtige Speicheranordnungen
NO171693C (no) Overstyringsmekanisme for ventil
MX155290A (es) Mejoras en valvula de compuerta
NO173795C (no) Sluseventil
DE69320574D1 (de) Statischer RAM-Speicher für Gattermatrixvorrichtungen
DE69332687D1 (de) Photopolymerisierbare zusammensetzung
DE69307398D1 (de) Programmierbare logische Zelle
DE69419987D1 (de) Küvettenform für Spektroskopie
DE69423504D1 (de) Photopolymerisierbare zusammensetzung
FR2727897B1 (fr) Mecanisme numeroteur
NO932087L (no) Avstandsstykke for armeringselementer
DE69121761D1 (de) Plattenförmiges Material für Schattenmaske
DE69321979D1 (de) Positive Photoresistzusammensetzung
NO174017C (no) Sluseventil

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee