DE69231374D1 - Verfahren zur Reparatur eines Ein-/Aufgabestiftes auf einer mehrschichtigen Leiterplatte - Google Patents

Verfahren zur Reparatur eines Ein-/Aufgabestiftes auf einer mehrschichtigen Leiterplatte

Info

Publication number
DE69231374D1
DE69231374D1 DE69231374T DE69231374T DE69231374D1 DE 69231374 D1 DE69231374 D1 DE 69231374D1 DE 69231374 T DE69231374 T DE 69231374T DE 69231374 T DE69231374 T DE 69231374T DE 69231374 D1 DE69231374 D1 DE 69231374D1
Authority
DE
Germany
Prior art keywords
repairing
procedure
input
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231374T
Other languages
English (en)
Other versions
DE69231374T2 (de
Inventor
Jun Inasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69231374D1 publication Critical patent/DE69231374D1/de
Publication of DE69231374T2 publication Critical patent/DE69231374T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10424—Frame holders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10704—Pin grid array [PGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/225—Correcting or repairing of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
DE69231374T 1991-10-11 1992-10-12 Verfahren zur Reparatur eines Ein-/Aufgabestiftes auf einer mehrschichtigen Leiterplatte Expired - Fee Related DE69231374T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3263801A JP2658672B2 (ja) 1991-10-11 1991-10-11 Ｉ／ｏピンの修理構造および修理方法

Publications (2)

Publication Number Publication Date
DE69231374D1 true DE69231374D1 (de) 2000-09-28
DE69231374T2 DE69231374T2 (de) 2001-04-12

Family

ID=17394445

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231374T Expired - Fee Related DE69231374T2 (de) 1991-10-11 1992-10-12 Verfahren zur Reparatur eines Ein-/Aufgabestiftes auf einer mehrschichtigen Leiterplatte

Country Status (5)

Country Link
US (1) US5373110A (de)
EP (1) EP0536802B1 (de)
JP (1) JP2658672B2 (de)
CA (1) CA2080094C (de)
DE (1) DE69231374T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07320800A (ja) * 1994-05-18 1995-12-08 Star Micronics Co Ltd 端子及びその製造方法
US6030857A (en) 1996-03-11 2000-02-29 Micron Technology, Inc. Method for application of spray adhesive to a leadframe for chip bonding
US6132798A (en) * 1998-08-13 2000-10-17 Micron Technology, Inc. Method for applying atomized adhesive to a leadframe for chip bonding
US5810926A (en) * 1996-03-11 1998-09-22 Micron Technology, Inc. Method and apparatus for applying atomized adhesive to a leadframe for chip bonding
CA2232523C (en) * 1996-07-22 2004-07-13 Honda Giken Kogyo Kabushiki Kaisha Plug-in type electronic control unit, structure of connection of wiring board with plug member, unit of connection of electronic part with wiring board, and process for mounting electronic part
DE69936319T2 (de) * 1998-12-16 2008-02-14 Ibiden Co., Ltd., Ogaki Leitender verbindungsstift und baugruppenplatte
JP3160583B2 (ja) * 1999-01-27 2001-04-25 日本特殊陶業株式会社 樹脂製基板
TW512653B (en) * 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
JP3550355B2 (ja) * 2000-04-13 2004-08-04 日本特殊陶業株式会社 ピン立設基板
US7071012B2 (en) * 2003-07-05 2006-07-04 Micron Technology, Inc. Methods relating to the reconstruction of semiconductor wafers for wafer-level processing
JP2009043844A (ja) * 2007-08-07 2009-02-26 Shinko Electric Ind Co Ltd リードピン付き配線基板およびリードピン
JP4993754B2 (ja) * 2008-02-22 2012-08-08 新光電気工業株式会社 Ｐｇａ型配線基板及びその製造方法
JP5290017B2 (ja) * 2008-03-28 2013-09-18 日本特殊陶業株式会社 多層配線基板及びその製造方法
EP2327122A4 (de) * 2008-09-15 2013-07-24 Pacific Aerospace & Electronics Inc Steckverbinderanordnungen mit keramischen einsätzen und leitfähigen pfaden und schnittstellen
JP5281346B2 (ja) * 2008-09-18 2013-09-04 新光電気工業株式会社 半導体装置及びその製造方法
JP5160390B2 (ja) * 2008-12-15 2013-03-13 新光電気工業株式会社 リードピン付配線基板及びその製造方法
JP5550280B2 (ja) * 2009-07-29 2014-07-16 京セラ株式会社 多層配線基板
JP5423621B2 (ja) * 2010-06-04 2014-02-19 株式会社デンソー 回路基板の端子接続構造
JP7476540B2 (ja) * 2020-01-23 2024-05-01 富士電機株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58110064A (ja) * 1981-12-23 1983-06-30 Nec Corp 半導体装置およびその製造方法
US5049434A (en) * 1984-04-30 1991-09-17 National Starch And Chemical Investment Holding Corporation Pre-patterned device substrate device-attach adhesive transfer system
US5191224A (en) * 1987-04-22 1993-03-02 Hitachi, Ltd. Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
JPH0258257A (ja) * 1988-08-23 1990-02-27 Ngk Spark Plug Co Ltd リード付き半導体パッケージ
JPH0766851B2 (ja) * 1989-07-12 1995-07-19 富士通株式会社 Ｉ／ｏピンの修復方法
JP2796394B2 (ja) * 1990-01-17 1998-09-10 株式会社日立製作所 入出力用ピンの補修接続法
US5173842A (en) * 1991-09-27 1992-12-22 International Business Machines Corporation Electrical assembly with deformable bridge printed circuit board
US5241454A (en) * 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package

Also Published As

Publication number Publication date
EP0536802A3 (en) 1993-07-21
DE69231374T2 (de) 2001-04-12
EP0536802A2 (de) 1993-04-14
CA2080094A1 (en) 1993-04-12
US5373110A (en) 1994-12-13
JP2658672B2 (ja) 1997-09-30
EP0536802B1 (de) 2000-08-23
CA2080094C (en) 1997-03-25
JPH05102382A (ja) 1993-04-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee