DE69228631T2 - Verfahren zur Kristallzüchtung eines III-V Verbindungshalbleiters - Google Patents

Verfahren zur Kristallzüchtung eines III-V Verbindungshalbleiters

Info

Publication number
DE69228631T2
DE69228631T2 DE69228631T DE69228631T DE69228631T2 DE 69228631 T2 DE69228631 T2 DE 69228631T2 DE 69228631 T DE69228631 T DE 69228631T DE 69228631 T DE69228631 T DE 69228631T DE 69228631 T2 DE69228631 T2 DE 69228631T2
Authority
DE
Germany
Prior art keywords
iii
compound semiconductor
crystal growth
growth
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69228631T
Other languages
English (en)
Other versions
DE69228631D1 (de
Inventor
Yasushi Shiraishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69228631D1 publication Critical patent/DE69228631D1/de
Publication of DE69228631T2 publication Critical patent/DE69228631T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/065—Gp III-V generic compounds-processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/104—Mask, movable
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
DE69228631T 1991-07-23 1992-07-23 Verfahren zur Kristallzüchtung eines III-V Verbindungshalbleiters Expired - Fee Related DE69228631T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3182636A JP2789861B2 (ja) 1991-07-23 1991-07-23 有機金属分子線エピタキシャル成長方法

Publications (2)

Publication Number Publication Date
DE69228631D1 DE69228631D1 (de) 1999-04-22
DE69228631T2 true DE69228631T2 (de) 1999-09-09

Family

ID=16121761

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69228631T Expired - Fee Related DE69228631T2 (de) 1991-07-23 1992-07-23 Verfahren zur Kristallzüchtung eines III-V Verbindungshalbleiters

Country Status (4)

Country Link
US (1) US5294565A (de)
EP (1) EP0524817B1 (de)
JP (1) JP2789861B2 (de)
DE (1) DE69228631T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335553A (ja) * 1995-06-07 1996-12-17 Nec Corp 選択エピタキシャル成長方法
US5591666A (en) * 1995-08-07 1997-01-07 Motorola Semiconductor device and method of fabrication
US6242327B1 (en) 1997-09-19 2001-06-05 Fujitsu Limited Compound semiconductor device having a reduced source resistance
US6911083B2 (en) * 2002-06-11 2005-06-28 Tokyo Institute Of Technology Method for producing powders made of gallium nitride and apparatus for producing the same
US7170147B2 (en) * 2003-07-28 2007-01-30 Lucent Technologies Inc. Dissipative isolation frames for active microelectronic devices, and methods of making such dissipative isolation frames
US7432161B2 (en) * 2005-01-07 2008-10-07 Stc.Unm Fabrication of optical-quality facets vertical to a (001) orientation substrate by selective epitaxial growth
CN100399590C (zh) * 2005-06-15 2008-07-02 上海蓝光科技有限公司 Mocvd生长氮化物发光二极管结构外延片的方法
DE602006004834D1 (de) * 2005-12-22 2009-03-05 Freiberger Compound Mat Gmbh Verfahren zum selektiven Maskieren von III-N-Schichten und zur Herstellung von selbsttragenden III-N-Schichten oder Bauelementen
US7790566B2 (en) * 2008-03-19 2010-09-07 International Business Machines Corporation Semiconductor surface treatment for epitaxial growth

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62177178A (ja) * 1986-01-31 1987-08-04 Hitachi Ltd 薄膜の製造方法
CA1313343C (en) * 1988-07-05 1993-02-02 Thomas F. Kuech Metal organic vapor phase epitaxial growth of group iii-v semiconductor materials
US5036022A (en) * 1988-07-05 1991-07-30 International Business Machines Corporation Metal organic vapor phase epitaxial growth of group III-V semiconductor materials

Also Published As

Publication number Publication date
JP2789861B2 (ja) 1998-08-27
DE69228631D1 (de) 1999-04-22
US5294565A (en) 1994-03-15
EP0524817A3 (en) 1993-08-18
JPH0529218A (ja) 1993-02-05
EP0524817A2 (de) 1993-01-27
EP0524817B1 (de) 1999-03-17

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee