DE69228333D1 - Trockenätzverfahren - Google Patents
TrockenätzverfahrenInfo
- Publication number
- DE69228333D1 DE69228333D1 DE69228333T DE69228333T DE69228333D1 DE 69228333 D1 DE69228333 D1 DE 69228333D1 DE 69228333 T DE69228333 T DE 69228333T DE 69228333 T DE69228333 T DE 69228333T DE 69228333 D1 DE69228333 D1 DE 69228333D1
- Authority
- DE
- Germany
- Prior art keywords
- etching process
- dry etching
- dry
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001312 dry etching Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3155454A JPH04354331A (ja) | 1991-05-31 | 1991-05-31 | ドライエッチング方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69228333D1 true DE69228333D1 (de) | 1999-03-18 |
DE69228333T2 DE69228333T2 (de) | 1999-09-02 |
Family
ID=15606399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69228333T Expired - Fee Related DE69228333T2 (de) | 1991-05-31 | 1992-05-26 | Trockenätzverfahren |
Country Status (5)
Country | Link |
---|---|
US (1) | US5312518A (de) |
EP (1) | EP0516053B1 (de) |
JP (1) | JPH04354331A (de) |
KR (1) | KR100229241B1 (de) |
DE (1) | DE69228333T2 (de) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5880036A (en) * | 1992-06-15 | 1999-03-09 | Micron Technology, Inc. | Method for enhancing oxide to nitride selectivity through the use of independent heat control |
JP3111661B2 (ja) * | 1992-07-24 | 2000-11-27 | ソニー株式会社 | ドライエッチング方法 |
US5651855A (en) * | 1992-07-28 | 1997-07-29 | Micron Technology, Inc. | Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits |
KR960008550B1 (en) * | 1992-12-31 | 1996-06-28 | Hyundai Electronics Ind | Contact plug manufacturing method using tungsten |
JPH06260396A (ja) * | 1993-03-02 | 1994-09-16 | Sony Corp | X線リソグラフィ用マスクの製造方法 |
US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
USRE39895E1 (en) | 1994-06-13 | 2007-10-23 | Renesas Technology Corp. | Semiconductor integrated circuit arrangement fabrication method |
US5811022A (en) | 1994-11-15 | 1998-09-22 | Mattson Technology, Inc. | Inductive plasma reactor |
JPH08255907A (ja) * | 1995-01-18 | 1996-10-01 | Canon Inc | 絶縁ゲート型トランジスタ及びその製造方法 |
US5983828A (en) * | 1995-10-13 | 1999-11-16 | Mattson Technology, Inc. | Apparatus and method for pulsed plasma processing of a semiconductor substrate |
US6794301B2 (en) | 1995-10-13 | 2004-09-21 | Mattson Technology, Inc. | Pulsed plasma processing of semiconductor substrates |
US6253704B1 (en) | 1995-10-13 | 2001-07-03 | Mattson Technology, Inc. | Apparatus and method for pulsed plasma processing of a semiconductor substrate |
KR100440418B1 (ko) * | 1995-12-12 | 2004-10-20 | 텍사스 인스트루먼츠 인코포레이티드 | 저압,저온의반도체갭충전처리방법 |
US5930585A (en) * | 1996-07-23 | 1999-07-27 | International Business Machines Corporation | Collar etch method to improve polysilicon strap integrity in DRAM chips |
US5882535A (en) * | 1997-02-04 | 1999-03-16 | Micron Technology, Inc. | Method for forming a hole in a semiconductor device |
US6303045B1 (en) * | 1997-03-20 | 2001-10-16 | Lam Research Corporation | Methods and apparatus for etching a nitride layer in a variable-gap plasma processing chamber |
US5965463A (en) * | 1997-07-03 | 1999-10-12 | Applied Materials, Inc. | Silane etching process |
TW436980B (en) * | 1998-07-08 | 2001-05-28 | United Microelectronics Corp | Method of local oxidation |
US5989979A (en) * | 1998-12-10 | 1999-11-23 | Chartered Semiconductor Manufacturing Ltd. | Method for controlling the silicon nitride profile during patterning using a novel plasma etch process |
EP1014434B1 (de) * | 1998-12-24 | 2008-03-26 | ATMEL Germany GmbH | Verfahren zum anisotropen plasmachemischen Trockenätzen von Siliziumnitrid-Schichten mittels eines Fluor-enthaltenden Gasgemisches |
JP3973819B2 (ja) * | 1999-03-08 | 2007-09-12 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
US7547635B2 (en) * | 2002-06-14 | 2009-06-16 | Lam Research Corporation | Process for etching dielectric films with improved resist and/or etch profile characteristics |
US20040171260A1 (en) * | 2002-06-14 | 2004-09-02 | Lam Research Corporation | Line edge roughness control |
US6886573B2 (en) | 2002-09-06 | 2005-05-03 | Air Products And Chemicals, Inc. | Plasma cleaning gas with lower global warming potential than SF6 |
KR100503814B1 (ko) * | 2003-02-04 | 2005-07-27 | 동부아남반도체 주식회사 | 반도체 소자의 게이트 형성 방법 |
US7232767B2 (en) * | 2003-04-01 | 2007-06-19 | Mattson Technology, Inc. | Slotted electrostatic shield modification for improved etch and CVD process uniformity |
FR2881876B1 (fr) * | 2005-02-07 | 2007-05-25 | Centre Nat Rech Scient | Procede d'oxydation planaire pour realiser un isolant enterre localise |
US7645707B2 (en) * | 2005-03-30 | 2010-01-12 | Lam Research Corporation | Etch profile control |
JP2008060238A (ja) * | 2006-08-30 | 2008-03-13 | Toshiba Corp | 半導体装置の製造方法 |
CN101330019B (zh) * | 2007-06-18 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | 通孔刻蚀方法及通孔区内钝化层去除方法 |
KR101562408B1 (ko) | 2007-09-27 | 2015-10-21 | 램 리써치 코포레이션 | Arc 레이어 개방을 이용한 라인 폭 거칠기 제어 |
CN101809721B (zh) | 2007-09-27 | 2013-03-06 | 朗姆研究公司 | 电介质蚀刻中的形貌控制 |
US9209178B2 (en) | 2013-11-25 | 2015-12-08 | International Business Machines Corporation | finFET isolation by selective cyclic etch |
JP6557588B2 (ja) * | 2015-12-04 | 2019-08-07 | 株式会社日立ハイテクノロジーズ | ドライエッチング方法 |
JP6604911B2 (ja) * | 2016-06-23 | 2019-11-13 | 東京エレクトロン株式会社 | エッチング処理方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4313782A (en) * | 1979-11-14 | 1982-02-02 | Rca Corporation | Method of manufacturing submicron channel transistors |
US4431477A (en) * | 1983-07-05 | 1984-02-14 | Matheson Gas Products, Inc. | Plasma etching with nitrous oxide and fluoro compound gas mixture |
JPS61136274A (ja) * | 1984-12-07 | 1986-06-24 | Toshiba Corp | 半導体装置 |
US4711698A (en) * | 1985-07-15 | 1987-12-08 | Texas Instruments Incorporated | Silicon oxide thin film etching process |
JP2669460B2 (ja) * | 1986-10-29 | 1997-10-27 | 株式会社日立製作所 | エツチング方法 |
EP0265584A3 (de) * | 1986-10-30 | 1989-12-06 | International Business Machines Corporation | Verfahren und Materialien zum Ätzen von Siliziumdioxid unter Verwendung eines Ätzstops aus Siliziumnitrid oder siliziumreichem Siliziumdioxid |
JPH0831441B2 (ja) * | 1986-12-04 | 1996-03-27 | 株式会社日立製作所 | 表面処理方法 |
JP2656479B2 (ja) * | 1987-01-14 | 1997-09-24 | 株式会社日立製作所 | ドライエツチング方法 |
US4956043A (en) * | 1987-05-25 | 1990-09-11 | Hitachi, Ltd. | Dry etching apparatus |
JPS6432627A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Ltd | Low-temperature dry etching method |
US4832787A (en) * | 1988-02-19 | 1989-05-23 | International Business Machines Corporation | Gas mixture and method for anisotropic selective etch of nitride |
US4836885A (en) * | 1988-05-03 | 1989-06-06 | International Business Machines Corporation | Planarization process for wide trench isolation |
JPH0360032A (ja) * | 1989-07-27 | 1991-03-15 | Sony Corp | ドライエッチング方法 |
EP0410635A1 (de) * | 1989-07-28 | 1991-01-30 | AT&T Corp. | Verfahren zum Aetzen von Oeffnungen mit abgeschrägten Flanken bei der Herstellung von Integrierten Halbleiterschaltungsbauelementen |
JPH03231426A (ja) * | 1990-02-07 | 1991-10-15 | Fujitsu Ltd | 半導体装置の製造方法 |
JP3006048B2 (ja) * | 1990-07-27 | 2000-02-07 | ソニー株式会社 | ドライエッチング方法 |
-
1991
- 1991-05-31 JP JP3155454A patent/JPH04354331A/ja not_active Withdrawn
-
1992
- 1992-05-26 DE DE69228333T patent/DE69228333T2/de not_active Expired - Fee Related
- 1992-05-26 EP EP92108858A patent/EP0516053B1/de not_active Expired - Lifetime
- 1992-05-29 US US07/891,448 patent/US5312518A/en not_active Expired - Fee Related
- 1992-05-30 KR KR1019920009372A patent/KR100229241B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69228333T2 (de) | 1999-09-02 |
EP0516053A3 (en) | 1993-05-26 |
KR100229241B1 (ko) | 1999-11-01 |
JPH04354331A (ja) | 1992-12-08 |
EP0516053B1 (de) | 1999-02-03 |
EP0516053A2 (de) | 1992-12-02 |
US5312518A (en) | 1994-05-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8339 | Ceased/non-payment of the annual fee |