DE69224872T2 - Entscheidungsgeführte Phasenverriegelte Schleife - Google Patents

Entscheidungsgeführte Phasenverriegelte Schleife

Info

Publication number
DE69224872T2
DE69224872T2 DE69224872T DE69224872T DE69224872T2 DE 69224872 T2 DE69224872 T2 DE 69224872T2 DE 69224872 T DE69224872 T DE 69224872T DE 69224872 T DE69224872 T DE 69224872T DE 69224872 T2 DE69224872 T2 DE 69224872T2
Authority
DE
Germany
Prior art keywords
decision
locked loop
phase locked
guided phase
guided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224872T
Other languages
English (en)
Other versions
DE69224872D1 (de
Inventor
Hiroaki Yada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69224872D1 publication Critical patent/DE69224872D1/de
Application granted granted Critical
Publication of DE69224872T2 publication Critical patent/DE69224872T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1488—Digital recording or reproducing using self-clocking codes characterised by the use of three levels
    • G11B20/1492—Digital recording or reproducing using self-clocking codes characterised by the use of three levels two levels are symmetric, in respect of the sign to the third level which is "zero"
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/16—Conversion to or from representation by pulses the pulses having three levels
    • H03M5/18—Conversion to or from representation by pulses the pulses having three levels two levels being symmetrical with respect to the third level, i.e. balanced bipolar ternary code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69224872T 1991-10-25 1992-10-22 Entscheidungsgeführte Phasenverriegelte Schleife Expired - Fee Related DE69224872T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3306643A JPH05120813A (ja) 1991-10-25 1991-10-25 位相ロツクループ回路

Publications (2)

Publication Number Publication Date
DE69224872D1 DE69224872D1 (de) 1998-04-30
DE69224872T2 true DE69224872T2 (de) 1998-10-22

Family

ID=17959574

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224872T Expired - Fee Related DE69224872T2 (de) 1991-10-25 1992-10-22 Entscheidungsgeführte Phasenverriegelte Schleife

Country Status (5)

Country Link
US (1) US5400364A (de)
EP (1) EP0538867B1 (de)
JP (1) JPH05120813A (de)
KR (1) KR930009256A (de)
DE (1) DE69224872T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10122621A1 (de) * 2001-05-10 2002-11-21 Infineon Technologies Ag Verfahren zum Bestimmen einer Referenztaktphase aus bandbegrenzten digitalen Datenströmen

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3558168B2 (ja) * 1992-10-30 2004-08-25 ソニー株式会社 光学式情報再生装置
JP3639618B2 (ja) 1994-08-25 2005-04-20 キヤノン株式会社 信号処理装置
US5696639A (en) * 1995-05-12 1997-12-09 Cirrus Logic, Inc. Sampled amplitude read channel employing interpolated timing recovery
US5760984A (en) * 1995-10-20 1998-06-02 Cirrus Logic, Inc. Cost reduced interpolated timing recovery in a sampled amplitude read channel
US6819514B1 (en) 1996-04-30 2004-11-16 Cirrus Logic, Inc. Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording
US5802118A (en) * 1996-07-29 1998-09-01 Cirrus Logic, Inc. Sub-sampled discrete time read channel for computer storage systems
JP3650984B2 (ja) * 1997-02-25 2005-05-25 ソニー株式会社 情報検出装置および方法
US5966415A (en) * 1997-06-13 1999-10-12 Cirrus Logic, Inc. Adaptive equalization in a sub-sampled read channel for a disk storage system
JP3337997B2 (ja) * 1999-03-29 2002-10-28 松下電器産業株式会社 周波数検出型位相同期回路
DE19941445A1 (de) * 1999-08-30 2001-03-01 Thomson Brandt Gmbh Phasendetektor für eine Phasenregelschleife
US6823133B1 (en) 1999-11-15 2004-11-23 Lexmark International, Inc. Apparatus and method for electronic control of DC motor using an all-digital phase-locked loop
US6904084B2 (en) * 2001-09-05 2005-06-07 Mediatek Incorporation Read channel apparatus and method for an optical storage system
US7245658B2 (en) * 2001-09-05 2007-07-17 Mediatek, Inc. Read channel apparatus for an optical storage system
US8379788B2 (en) * 2010-06-18 2013-02-19 Nec Laboratories America, Inc. Systems and methods for performing parallel digital phase-locked-loop

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992410A (ja) * 1982-11-17 1984-05-28 Sony Corp デ−タ検出装置
JPH069106B2 (ja) * 1987-07-22 1994-02-02 シャープ株式会社 ディジタルデ−タ検出器
DE3778549D1 (de) * 1987-11-13 1992-05-27 Ibm Schnelle takterfassung fuer partial-response-signalisierung.
JPH01296733A (ja) * 1988-05-25 1989-11-30 Toshiba Corp ディジタル形位相同期回路
JPH03166839A (ja) * 1989-11-27 1991-07-18 Matsushita Electric Ind Co Ltd ディジタル情報検出装置
US5272730A (en) * 1991-12-20 1993-12-21 Vlsi Technology, Inc. Digital phase-locked loop filter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10122621A1 (de) * 2001-05-10 2002-11-21 Infineon Technologies Ag Verfahren zum Bestimmen einer Referenztaktphase aus bandbegrenzten digitalen Datenströmen
DE10122621B4 (de) * 2001-05-10 2006-07-27 Infineon Technologies Ag Verfahren zum Bestimmen einer Referenztaktphase aus bandbegrenzten digitalen Datenströmen
US7194045B2 (en) 2001-05-10 2007-03-20 Infineon Technologies Ag Method for determining a reference clock phase from band-limited digital data streams

Also Published As

Publication number Publication date
US5400364A (en) 1995-03-21
EP0538867A2 (de) 1993-04-28
DE69224872D1 (de) 1998-04-30
KR930009256A (ko) 1993-05-22
EP0538867A3 (en) 1995-09-20
JPH05120813A (ja) 1993-05-18
EP0538867B1 (de) 1998-03-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee