DE69224174D1 - Phasenregelschleife mit hoher Zuverlässigkeit - Google Patents

Phasenregelschleife mit hoher Zuverlässigkeit

Info

Publication number
DE69224174D1
DE69224174D1 DE69224174T DE69224174T DE69224174D1 DE 69224174 D1 DE69224174 D1 DE 69224174D1 DE 69224174 T DE69224174 T DE 69224174T DE 69224174 T DE69224174 T DE 69224174T DE 69224174 D1 DE69224174 D1 DE 69224174D1
Authority
DE
Germany
Prior art keywords
high reliability
locked loop
phase locked
phase
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224174T
Other languages
English (en)
Other versions
DE69224174T2 (de
Inventor
Alan C Rogers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69224174D1 publication Critical patent/DE69224174D1/de
Publication of DE69224174T2 publication Critical patent/DE69224174T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015Layout of the delay element
    • H03K2005/00195Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69224174T 1991-12-19 1992-11-18 Phasenregelschleife mit hoher Zuverlässigkeit Expired - Fee Related DE69224174T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/812,125 US5220293A (en) 1991-12-19 1991-12-19 High reliability phase-locked loop

Publications (2)

Publication Number Publication Date
DE69224174D1 true DE69224174D1 (de) 1998-02-26
DE69224174T2 DE69224174T2 (de) 1998-08-20

Family

ID=25208587

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224174T Expired - Fee Related DE69224174T2 (de) 1991-12-19 1992-11-18 Phasenregelschleife mit hoher Zuverlässigkeit

Country Status (5)

Country Link
US (1) US5220293A (de)
EP (1) EP0547770B1 (de)
JP (1) JP3292963B2 (de)
KR (1) KR100214168B1 (de)
DE (1) DE69224174T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864572A (en) * 1996-08-26 1999-01-26 Sun Microsystems, Inc. Oscillator runaway detect and reset circuit for PLL clock generator
KR19980042114A (ko) * 1996-11-11 1998-08-17 가나이 츠토무 위상록루프회로를 갖는 시스템
US6411237B1 (en) 1997-10-21 2002-06-25 Emhiser Research Ltd Nonlinear digital-to-analog converters
CA2308209C (en) 1997-10-21 2004-03-09 Lloyd Lynn Lautzenhiser Adaptive frequency-hopping oscillators
US6111442A (en) * 1998-03-09 2000-08-29 International Business Machines Corporation Phase-locked loop circuit with dynamic backup
US6718473B1 (en) 2000-09-26 2004-04-06 Sun Microsystems, Inc. Method and apparatus for reducing power consumption
US6608476B1 (en) 2000-09-26 2003-08-19 Sun Microsystems, Inc. Method and apparatus for reducing power consumption
US6748546B1 (en) 2000-09-26 2004-06-08 Sun Microsystems, Inc. Method and apparatus for reducing power consumption
US6700421B1 (en) 2000-09-26 2004-03-02 Sun Microsystems, Inc. Method and apparatus for reducing power consumption
US6728890B1 (en) 2000-09-26 2004-04-27 Sun Microsystems, Inc. Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component
US6836824B1 (en) 2000-09-26 2004-12-28 Sun Microsystems, Inc. Method and apparatus for reducing power consumption in a cache memory system
US6969984B2 (en) * 2000-12-21 2005-11-29 Tropian, Inc. Direct phase and frequency demodulation
TW583837B (en) * 2003-05-06 2004-04-11 Realtek Semiconductor Corp Phase frequency detector applied in digital PLL system
JP2006157630A (ja) * 2004-11-30 2006-06-15 Nec Electronics Corp Pll回路
US8866556B2 (en) * 2009-02-27 2014-10-21 Analog Bits, Inc. Phase shift phase locked loop
US7940088B1 (en) 2009-03-31 2011-05-10 Pmc-Sierra, Inc. High speed phase frequency detector
US8742957B2 (en) 2010-12-15 2014-06-03 Analog Bits, Inc. Multi-variable multi-wire interconnect
DE102016115657A1 (de) * 2016-08-23 2018-03-01 Infineon Technologies Ag Phasenregelkreis
KR102321926B1 (ko) 2019-03-21 2021-11-04 강성실 리프트 재배기

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322643A (en) * 1980-04-28 1982-03-30 Rca Corporation Digital phase comparator with improved sensitivity for small phase differences
JPS59227A (ja) * 1982-06-25 1984-01-05 Pioneer Electronic Corp Pll回路の引込制御装置
IL71718A (en) * 1984-05-01 1990-01-18 Tadiran Ltd Millimeter wave frequency synthesizer
US4787097A (en) * 1987-02-11 1988-11-22 International Business Machines Corporation NRZ phase-locked loop circuit with associated monitor and recovery circuitry
US4806934A (en) * 1987-04-20 1989-02-21 Raytheon Company Tracking circuit for following objects through antenna nulls
US4788512A (en) * 1987-06-05 1988-11-29 Rockwell International Corporation Gain maintenance apparatus for use with a high gain amplifier incorporated in a closed loop feedback system
JP2568110B2 (ja) * 1988-07-15 1996-12-25 パイオニア株式会社 フェーズロックドループ回路
US5057794A (en) * 1991-02-26 1991-10-15 Level One Communications, Inc. Phase-locked loop with pattern controlled bandwidth circuit

Also Published As

Publication number Publication date
EP0547770B1 (de) 1998-01-21
JP3292963B2 (ja) 2002-06-17
EP0547770A1 (de) 1993-06-23
US5220293A (en) 1993-06-15
KR100214168B1 (ko) 1999-08-02
JPH05315948A (ja) 1993-11-26
KR930015363A (ko) 1993-07-24
DE69224174T2 (de) 1998-08-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee