DE3885116T2 - Phasenregelschleifen. - Google Patents

Phasenregelschleifen.

Info

Publication number
DE3885116T2
DE3885116T2 DE88300441T DE3885116T DE3885116T2 DE 3885116 T2 DE3885116 T2 DE 3885116T2 DE 88300441 T DE88300441 T DE 88300441T DE 3885116 T DE3885116 T DE 3885116T DE 3885116 T2 DE3885116 T2 DE 3885116T2
Authority
DE
Germany
Prior art keywords
phase locked
locked loops
loops
phase
locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88300441T
Other languages
English (en)
Other versions
DE3885116D1 (de
Inventor
Richard Miller Waltham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thorn EMI PLC
Original Assignee
Thorn EMI PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thorn EMI PLC filed Critical Thorn EMI PLC
Application granted granted Critical
Publication of DE3885116D1 publication Critical patent/DE3885116D1/de
Publication of DE3885116T2 publication Critical patent/DE3885116T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
DE88300441T 1987-01-24 1988-01-20 Phasenregelschleifen. Expired - Fee Related DE3885116T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB878701573A GB8701573D0 (en) 1987-01-24 1987-01-24 Phase-locked loops

Publications (2)

Publication Number Publication Date
DE3885116D1 DE3885116D1 (de) 1993-12-02
DE3885116T2 true DE3885116T2 (de) 1994-04-28

Family

ID=10611173

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88300441T Expired - Fee Related DE3885116T2 (de) 1987-01-24 1988-01-20 Phasenregelschleifen.

Country Status (5)

Country Link
US (1) US4791378A (de)
EP (1) EP0277726B1 (de)
JP (1) JPS63200618A (de)
DE (1) DE3885116T2 (de)
GB (1) GB8701573D0 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855683A (en) * 1987-11-18 1989-08-08 Bell Communications Research, Inc. Digital phase locked loop with bounded jitter
US5390207A (en) * 1990-11-28 1995-02-14 Novatel Communications Ltd. Pseudorandom noise ranging receiver which compensates for multipath distortion by dynamically adjusting the time delay spacing between early and late correlators
US5101416A (en) * 1990-11-28 1992-03-31 Novatel Comunications Ltd. Multi-channel digital receiver for global positioning system
US5249204A (en) * 1991-08-12 1993-09-28 Motorola, Inc. Circuit and method for phase error correction in a digital receiver
JPH0591522A (ja) * 1991-09-30 1993-04-09 Toshiba Corp デイジタル発振器及びこれを用いた色副搬送波再生回路
US5402450A (en) * 1992-01-22 1995-03-28 Trimble Navigation Signal timing synchronizer
US5414729A (en) * 1992-01-24 1995-05-09 Novatel Communications Ltd. Pseudorandom noise ranging receiver which compensates for multipath distortion by making use of multiple correlator time delay spacing
JP3245925B2 (ja) * 1992-02-19 2002-01-15 ソニー株式会社 デジタルｐｌｌ回路
DE69415378T2 (de) * 1993-04-05 1999-06-17 Koninkl Philips Electronics Nv Digitaler Phasenregelkreis
US5479457A (en) * 1993-08-27 1995-12-26 Vlsi Technology Inc. Method and apparatus for attenuating jitter in a digital transmission line
US5742191A (en) * 1993-12-08 1998-04-21 Thomson Consumer Electronics, Inc. D/A for controlling an oscillator in a phase locked loop
JP2806239B2 (ja) * 1993-12-28 1998-09-30 三菱電機株式会社 周波数シンセサイザ
JP3141760B2 (ja) * 1995-12-06 2001-03-05 ヤマハ株式会社 デジタルｐｌｌ回路
DE19727582A1 (de) * 1997-06-28 1999-01-07 Bosch Gmbh Robert Verfahren und Schaltungsanordnung zur Synchronisation eines Zeittaktes mit in einem Zeitraster auftretenden Ereignissen
US7124153B2 (en) 2002-03-18 2006-10-17 Genesis Microchip Inc. Frequency converter and methods of use thereof
US7205798B1 (en) * 2004-05-28 2007-04-17 Intersil Americas Inc. Phase error correction circuit for a high speed frequency synthesizer
US7135933B2 (en) * 2004-09-29 2006-11-14 Intelliserv, Inc. System for adjusting frequency of electrical output pulses derived from an oscillator
CN111030687B (zh) * 2019-12-31 2023-07-18 南华大学 基于快速全加器的全数字锁相环及锁相控制方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2854039C2 (de) * 1978-12-12 1984-07-12 Heinrich-Hertz-Institut für Nachrichtentechnik Berlin GmbH, 1000 Berlin Verfahren und Phasenregelkreis zum Synchronisieren eines Ausgangssignals mit einem Eingangssignal unregelmäßiger und/oder stark ausgedünnter Flankendichte
US4577163A (en) * 1984-07-09 1986-03-18 Honeywell Inc. Digital phase locked loop
DE3432314A1 (de) * 1984-09-03 1986-03-13 Philips Patentverwaltung Gmbh, 2000 Hamburg Schaltungsanordnung zum ableiten digitaler farbsignale aus einem analogen fernsehsignal

Also Published As

Publication number Publication date
GB8701573D0 (en) 1987-02-25
EP0277726A3 (en) 1990-02-07
EP0277726A2 (de) 1988-08-10
US4791378A (en) 1988-12-13
DE3885116D1 (de) 1993-12-02
JPS63200618A (ja) 1988-08-18
EP0277726B1 (de) 1993-10-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee