DE69213928D1 - Verdrahtung auf Wolfram-Plomben - Google Patents

Verdrahtung auf Wolfram-Plomben

Info

Publication number
DE69213928D1
DE69213928D1 DE69213928T DE69213928T DE69213928D1 DE 69213928 D1 DE69213928 D1 DE 69213928D1 DE 69213928 T DE69213928 T DE 69213928T DE 69213928 T DE69213928 T DE 69213928T DE 69213928 D1 DE69213928 D1 DE 69213928D1
Authority
DE
Germany
Prior art keywords
tungsten
seals
wiring
tungsten seals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69213928T
Other languages
English (en)
Other versions
DE69213928T2 (de
Inventor
Maria Santina Marangon
Andrea Marmiroli
Giorgio Desanti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE69213928D1 publication Critical patent/DE69213928D1/de
Publication of DE69213928T2 publication Critical patent/DE69213928T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/963—Removing process residues from vertical substrate surfaces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69213928T 1992-05-27 1992-05-27 Verdrahtung auf Wolfram-Plomben Expired - Fee Related DE69213928T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92830265A EP0571691B1 (de) 1992-05-27 1992-05-27 Verdrahtung auf Wolfram-Plomben

Publications (2)

Publication Number Publication Date
DE69213928D1 true DE69213928D1 (de) 1996-10-24
DE69213928T2 DE69213928T2 (de) 1997-03-13

Family

ID=8212110

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69213928T Expired - Fee Related DE69213928T2 (de) 1992-05-27 1992-05-27 Verdrahtung auf Wolfram-Plomben

Country Status (4)

Country Link
US (2) US5407861A (de)
EP (1) EP0571691B1 (de)
JP (1) JPH0637033A (de)
DE (1) DE69213928T2 (de)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0571691B1 (de) * 1992-05-27 1996-09-18 STMicroelectronics S.r.l. Verdrahtung auf Wolfram-Plomben
JP3179212B2 (ja) * 1992-10-27 2001-06-25 日本電気株式会社 半導体装置の製造方法
US5776827A (en) * 1993-08-27 1998-07-07 Yamaha Corporation Wiring-forming method
JPH08191104A (ja) 1995-01-11 1996-07-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2710221B2 (ja) * 1995-01-25 1998-02-10 日本電気株式会社 半導体装置及びその製造方法
US5521121A (en) * 1995-04-03 1996-05-28 Taiwan Semiconductor Manufacturing Company Oxygen plasma etch process post contact layer etch back
US5496773A (en) * 1995-04-28 1996-03-05 Micron Technology, Inc. Semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner electrically conductive node and an elevationally outer electrically conductive node
JPH08321545A (ja) * 1995-05-24 1996-12-03 Yamaha Corp 配線形成法
JP3538970B2 (ja) * 1995-05-24 2004-06-14 ヤマハ株式会社 配線形成法
KR100218728B1 (ko) * 1995-11-01 1999-09-01 김영환 반도체 소자의 금속 배선 제조방법
JPH09148431A (ja) * 1995-11-21 1997-06-06 Nec Corp 半導体装置の製造方法
US5712207A (en) * 1996-02-29 1998-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Profile improvement of a metal interconnect structure on a tungsten plug
US5904559A (en) * 1996-03-06 1999-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional contact or via structure with multiple sidewall contacts
US5622894A (en) * 1996-03-15 1997-04-22 Taiwan Semiconductor Manufacturing Company Ltd Process to minimize a seam in tungsten filled contact holes
US5926359A (en) 1996-04-01 1999-07-20 International Business Machines Corporation Metal-insulator-metal capacitor
JPH09298238A (ja) * 1996-05-08 1997-11-18 Yamaha Corp 配線形成方法
US5801096A (en) * 1996-06-03 1998-09-01 Taiwan Semiconductor Manufacturing Company Ltd. Self-aligned tungsen etch back process to minimize seams in tungsten plugs
US5641710A (en) * 1996-06-10 1997-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Post tungsten etch back anneal, to improve aluminum step coverage
US5700726A (en) * 1996-06-21 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Multi-layered tungsten depositions for contact hole filling
JPH1064848A (ja) * 1996-08-13 1998-03-06 Toshiba Corp 半導体装置の製造装置および製造方法
KR100221656B1 (ko) * 1996-10-23 1999-09-15 구본준 배선 형성 방법
US5804502A (en) * 1997-01-16 1998-09-08 Vlsi Technology, Inc. Tungsten plugs for integrated circuits and methods for making same
US5688718A (en) * 1997-02-03 1997-11-18 Taiwan Semiconductor Manufacturing Company Ltd Method of CVD TiN barrier layer integration
US7943505B2 (en) * 1997-03-14 2011-05-17 Micron Technology, Inc. Advanced VLSI metallization
JP3111924B2 (ja) * 1997-04-11 2000-11-27 日本電気株式会社 半導体装置の製造方法
US5915202A (en) * 1997-05-15 1999-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Blanket etching process for formation of tungsten plugs
JP3602294B2 (ja) * 1997-05-28 2004-12-15 株式会社ルネサステクノロジ 半導体メモリおよび情報記憶装置
US5994775A (en) * 1997-09-17 1999-11-30 Lsi Logic Corporation Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same
KR100292943B1 (ko) 1998-03-25 2001-09-17 윤종용 디램장치의제조방법
US6316834B1 (en) 1998-06-12 2001-11-13 Vlsi Technology, Inc. Tungsten plugs for integrated circuits and method for making same
US6103623A (en) * 1998-10-05 2000-08-15 Vanguard International Semiconductor Corporation Method for fabricating a tungsten plug structure and an overlying interconnect metal structure without a tungsten etch back or CMP procedure
US20010013660A1 (en) * 1999-01-04 2001-08-16 Peter Richard Duncombe Beol decoupling capacitor
US6306757B1 (en) * 1999-06-02 2001-10-23 United Microelectronics Corp. Method for forming a multilevel interconnect
US20030015496A1 (en) * 1999-07-22 2003-01-23 Sujit Sharan Plasma etching process
KR100335120B1 (ko) * 1999-08-25 2002-05-04 박종섭 반도체 소자의 금속 배선 형성 방법
JP4342075B2 (ja) 2000-03-28 2009-10-14 株式会社東芝 半導体装置およびその製造方法
US6352924B1 (en) * 2000-06-05 2002-03-05 Taiwan Semiconductor Manufacturing Company Rework method for wafers that trigger WCVD backside alarm
US6872668B1 (en) * 2000-09-26 2005-03-29 Integrated Device Technology, Inc. Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure
JP2003163263A (ja) * 2001-11-27 2003-06-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
US7836211B2 (en) 2003-01-21 2010-11-16 Emulex Design And Manufacturing Corporation Shared input/output load-store architecture
US8102843B2 (en) 2003-01-21 2012-01-24 Emulex Design And Manufacturing Corporation Switching apparatus and method for providing shared I/O within a load-store fabric
US7953074B2 (en) 2003-01-21 2011-05-31 Emulex Design And Manufacturing Corporation Apparatus and method for port polarity initialization in a shared I/O device
US7698483B2 (en) 2003-01-21 2010-04-13 Nextio, Inc. Switching apparatus and method for link initialization in a shared I/O environment
US6855638B2 (en) * 2003-03-24 2005-02-15 Union Semiconductor Technology Corporation Process to pattern thick TiW metal layers using uniform and selective etching
US7323410B2 (en) * 2005-08-08 2008-01-29 International Business Machines Corporation Dry etchback of interconnect contacts
US8030215B1 (en) * 2008-02-19 2011-10-04 Marvell International Ltd. Method for creating ultra-high-density holes and metallization
US8883637B2 (en) * 2011-06-30 2014-11-11 Novellus Systems, Inc. Systems and methods for controlling etch selectivity of various materials
JP6299406B2 (ja) * 2013-12-19 2018-03-28 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
US4980018A (en) * 1989-11-14 1990-12-25 Intel Corporation Plasma etching process for refractory metal vias
JPH0480917A (ja) * 1990-07-24 1992-03-13 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH04257227A (ja) * 1991-02-08 1992-09-11 Sony Corp 配線形成方法
US5164330A (en) * 1991-04-17 1992-11-17 Intel Corporation Etchback process for tungsten utilizing a NF3/AR chemistry
EP0571691B1 (de) * 1992-05-27 1996-09-18 STMicroelectronics S.r.l. Verdrahtung auf Wolfram-Plomben
JPH06112172A (ja) * 1992-09-25 1994-04-22 Sony Corp ドライエッチング方法
JP3179212B2 (ja) * 1992-10-27 2001-06-25 日本電気株式会社 半導体装置の製造方法
US5521119A (en) * 1994-07-13 1996-05-28 Taiwan Semiconductor Manufacturing Co. Post treatment of tungsten etching back
US5514622A (en) * 1994-08-29 1996-05-07 Cypress Semiconductor Corporation Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole

Also Published As

Publication number Publication date
US5407861A (en) 1995-04-18
JPH0637033A (ja) 1994-02-10
EP0571691B1 (de) 1996-09-18
US5786272A (en) 1998-07-28
EP0571691A1 (de) 1993-12-01
DE69213928T2 (de) 1997-03-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee