DE69213032D1 - Halbleiteranordnung zur Verbesserung der Hochfrequenzcharakteristiken und zur Vermeidung von Rissen im Chip - Google Patents

Halbleiteranordnung zur Verbesserung der Hochfrequenzcharakteristiken und zur Vermeidung von Rissen im Chip

Info

Publication number
DE69213032D1
DE69213032D1 DE69213032T DE69213032T DE69213032D1 DE 69213032 D1 DE69213032 D1 DE 69213032D1 DE 69213032 T DE69213032 T DE 69213032T DE 69213032 T DE69213032 T DE 69213032T DE 69213032 D1 DE69213032 D1 DE 69213032D1
Authority
DE
Germany
Prior art keywords
chip
improve
frequency characteristics
semiconductor arrangement
avoid cracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69213032T
Other languages
English (en)
Other versions
DE69213032T2 (de
Inventor
Masakazu Kojima
Yoshio Aoki
Seigo Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Quantum Devices Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Quantum Devices Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Quantum Devices Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69213032D1 publication Critical patent/DE69213032D1/de
Publication of DE69213032T2 publication Critical patent/DE69213032T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • H01L2924/30111Impedance matching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE1992613032 1991-01-10 1992-01-03 Halbleiteranordnung zur Verbesserung der Hochfrequenzcharakteristiken und zur Vermeidung von Rissen im Chip Expired - Lifetime DE69213032T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3001651A JPH04252036A (ja) 1991-01-10 1991-01-10 半導体装置

Publications (2)

Publication Number Publication Date
DE69213032D1 true DE69213032D1 (de) 1996-10-02
DE69213032T2 DE69213032T2 (de) 1997-01-16

Family

ID=11507425

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1992613032 Expired - Lifetime DE69213032T2 (de) 1991-01-10 1992-01-03 Halbleiteranordnung zur Verbesserung der Hochfrequenzcharakteristiken und zur Vermeidung von Rissen im Chip

Country Status (5)

Country Link
US (1) US5287072A (de)
EP (1) EP0494625B1 (de)
JP (1) JPH04252036A (de)
CA (1) CA2058672C (de)
DE (1) DE69213032T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2580966B2 (ja) * 1993-08-05 1997-02-12 日本電気株式会社 半導体装置
DE19522364C1 (de) * 1995-06-20 1996-07-04 Siemens Ag Halbleiter-Bauelement
JPH09153499A (ja) * 1995-11-30 1997-06-10 Nec Corp 半導体装置
JP3152145B2 (ja) * 1996-02-28 2001-04-03 日本電気株式会社 半導体装置
US5942900A (en) * 1996-12-17 1999-08-24 Lexmark International, Inc. Method of fault detection in ink jet printhead heater chips
JP3287279B2 (ja) * 1997-09-25 2002-06-04 日本電気株式会社 半導体チップ、および該半導体チップが実装された半導体装置
US6081006A (en) * 1998-08-13 2000-06-27 Cisco Systems, Inc. Reduced size field effect transistor
US6774416B2 (en) * 2001-07-16 2004-08-10 Nanowave, Inc Small area cascode FET structure operating at mm-wave frequencies
WO2004049449A1 (ja) * 2002-11-25 2004-06-10 National Institute Of Advanced Industrial Science And Technology 半導体装置、およびその半導体装置を用いた電力変換器、駆動用インバータ、汎用インバータ、大電力高周波通信機器
JP2005183770A (ja) * 2003-12-22 2005-07-07 Mitsubishi Electric Corp 高周波用半導体装置
US20060202320A1 (en) * 2005-03-10 2006-09-14 Schaffer Christopher P Power semiconductor package
JP6488720B2 (ja) * 2015-01-23 2019-03-27 三菱電機株式会社 半導体装置
JPWO2020195808A1 (de) * 2019-03-26 2020-10-01

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1254302A (en) * 1968-03-11 1971-11-17 Associated Semiconductor Mft Improvements in insulated gate field effect transistors
US3969745A (en) * 1974-09-18 1976-07-13 Texas Instruments Incorporated Interconnection in multi element planar structures
US4104672A (en) * 1976-10-29 1978-08-01 Bell Telephone Laboratories, Incorporated High power gallium arsenide schottky barrier field effect transistor
JPS55108775A (en) * 1979-02-09 1980-08-21 Fujitsu Ltd Semiconductor device
US4343015A (en) * 1980-05-14 1982-08-03 General Electric Company Vertical channel field effect transistor
US4725747A (en) * 1986-08-29 1988-02-16 Texas Instruments Incorporated Integrated circuit distributed geometry to reduce switching noise
JP2633562B2 (ja) * 1987-05-27 1997-07-23 株式会社東芝 半導体集積回路
US5025296A (en) * 1988-02-29 1991-06-18 Motorola, Inc. Center tapped FET
JPH0226033A (ja) * 1988-07-14 1990-01-29 Nec Corp 高周波高出力トランジスタ
US5023677A (en) * 1990-05-02 1991-06-11 Texas Instruments Incorporated Low parasitic FET topology for power and low noise GaAs FETs

Also Published As

Publication number Publication date
EP0494625B1 (de) 1996-08-28
US5287072A (en) 1994-02-15
DE69213032T2 (de) 1997-01-16
EP0494625A1 (de) 1992-07-15
CA2058672A1 (en) 1992-07-11
CA2058672C (en) 1996-04-02
JPH04252036A (ja) 1992-09-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE