DE69211329D1 - Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur - Google Patents

Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur

Info

Publication number
DE69211329D1
DE69211329D1 DE69211329T DE69211329T DE69211329D1 DE 69211329 D1 DE69211329 D1 DE 69211329D1 DE 69211329 T DE69211329 T DE 69211329T DE 69211329 T DE69211329 T DE 69211329T DE 69211329 D1 DE69211329 D1 DE 69211329D1
Authority
DE
Germany
Prior art keywords
film
structure produced
pfet devices
planar thin
producing pseudo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69211329T
Other languages
English (en)
Other versions
DE69211329T2 (de
Inventor
Carl Cederbaum
Roland Chanclou
Myriam Combes
Patrick Mone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69211329D1 publication Critical patent/DE69211329D1/de
Publication of DE69211329T2 publication Critical patent/DE69211329T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69211329T 1992-03-27 1992-03-27 Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur Expired - Fee Related DE69211329T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92480048A EP0562207B1 (de) 1992-03-27 1992-03-27 Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur

Publications (2)

Publication Number Publication Date
DE69211329D1 true DE69211329D1 (de) 1996-07-11
DE69211329T2 DE69211329T2 (de) 1996-11-28

Family

ID=8211782

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69211329T Expired - Fee Related DE69211329T2 (de) 1992-03-27 1992-03-27 Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur

Country Status (4)

Country Link
US (1) US5320975A (de)
EP (1) EP0562207B1 (de)
JP (1) JP2520556B2 (de)
DE (1) DE69211329T2 (de)

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US5879972A (en) * 1995-07-13 1999-03-09 Nkk Corporation SRAM device and method of manufacturing the same
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US6087254A (en) * 1996-07-16 2000-07-11 Micron Technology, Inc. Technique for elimination of pitting on silicon substrate during gate stack etch
US6613673B2 (en) 1996-07-16 2003-09-02 Micron Technology, Inc. Technique for elimination of pitting on silicon substrate during gate stack etch
US7041548B1 (en) * 1996-07-16 2006-05-09 Micron Technology, Inc. Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof
US5818750A (en) * 1996-07-31 1998-10-06 Micron Technology, Inc. Static memory cell
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US6174764B1 (en) * 1997-05-12 2001-01-16 Micron Technology, Inc. Process for manufacturing integrated circuit SRAM
US6541164B1 (en) * 1997-10-22 2003-04-01 Applied Materials, Inc. Method for etching an anti-reflective coating
US6103632A (en) * 1997-10-22 2000-08-15 Applied Material Inc. In situ Etching of inorganic dielectric anti-reflective coating from a substrate
US6051881A (en) * 1997-12-05 2000-04-18 Advanced Micro Devices Forming local interconnects in integrated circuits
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US6294416B1 (en) * 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6271555B1 (en) 1998-03-31 2001-08-07 International Business Machines Corporation Borderless wordline for DRAM cell
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JP2009177200A (ja) * 1998-05-01 2009-08-06 Sony Corp 半導体記憶装置
US5982691A (en) * 1998-09-30 1999-11-09 Advanced Micro Devices, Inc. Method and apparatus for determining the robustness of memory cells to induced soft errors using equivalent diodes
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US6091630A (en) * 1999-09-10 2000-07-18 Stmicroelectronics, Inc. Radiation hardened semiconductor memory
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KR100474546B1 (ko) * 1999-12-24 2005-03-08 주식회사 하이닉스반도체 반도체소자의 제조방법
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US6368986B1 (en) * 2000-08-31 2002-04-09 Micron Technology, Inc. Use of selective ozone TEOS oxide to create variable thickness layers and spacers
US6503851B2 (en) * 2000-08-31 2003-01-07 Micron Technology, Inc. Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off
JP2002176112A (ja) * 2000-12-08 2002-06-21 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
DE10131492B4 (de) * 2001-06-29 2006-09-14 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeichervorrichtung
US6730553B2 (en) * 2001-08-30 2004-05-04 Micron Technology, Inc. Methods for making semiconductor structures having high-speed areas and high-density areas
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JP4577680B2 (ja) * 2004-04-13 2010-11-10 エルピーダメモリ株式会社 半導体装置の製造方法
KR100683852B1 (ko) * 2004-07-02 2007-02-15 삼성전자주식회사 반도체 소자의 마스크롬 소자 및 그 형성 방법
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Also Published As

Publication number Publication date
EP0562207A1 (de) 1993-09-29
DE69211329T2 (de) 1996-11-28
US5320975A (en) 1994-06-14
EP0562207B1 (de) 1996-06-05
JP2520556B2 (ja) 1996-07-31
JPH0613582A (ja) 1994-01-21

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee