DE68911973D1 - Anordnung und Verfahren zum Herstellen einer Anordnung. - Google Patents

Anordnung und Verfahren zum Herstellen einer Anordnung.

Info

Publication number
DE68911973D1
DE68911973D1 DE89200818T DE68911973T DE68911973D1 DE 68911973 D1 DE68911973 D1 DE 68911973D1 DE 89200818 T DE89200818 T DE 89200818T DE 68911973 T DE68911973 T DE 68911973T DE 68911973 D1 DE68911973 D1 DE 68911973D1
Authority
DE
Germany
Prior art keywords
arrangement
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89200818T
Other languages
English (en)
Other versions
DE68911973T2 (de
Inventor
Der Kolk Gerrit Jan Van
Theunis Siemen Baller
Bernard Dam
Reus Roger De
Frans Willem Saris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE68911973D1 publication Critical patent/DE68911973D1/de
Application granted granted Critical
Publication of DE68911973T2 publication Critical patent/DE68911973T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
    • H10N60/0576—Processes for depositing or forming copper oxide superconductor layers characterised by the substrate
    • H10N60/0632—Intermediate layers, e.g. for growth control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0744—Manufacture or deposition of electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/70—High TC, above 30 k, superconducting device, article, or structured stock
    • Y10S505/701—Coated or thin film device, i.e. active or passive
    • Y10S505/702—Josephson junction present
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/825—Apparatus per se, device per se, or process of making or operating same
    • Y10S505/873—Active solid-state device
    • Y10S505/874—Active solid-state device with josephson junction, e.g. squid

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE68911973T 1988-04-05 1989-03-30 Anordnung und Verfahren zum Herstellen einer Anordnung. Expired - Fee Related DE68911973T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8800857A NL8800857A (nl) 1988-04-05 1988-04-05 Inrichting en werkwijze voor het vervaardigen van een inrichting.

Publications (2)

Publication Number Publication Date
DE68911973D1 true DE68911973D1 (de) 1994-02-17
DE68911973T2 DE68911973T2 (de) 1994-07-07

Family

ID=19852063

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68911973T Expired - Fee Related DE68911973T2 (de) 1988-04-05 1989-03-30 Anordnung und Verfahren zum Herstellen einer Anordnung.

Country Status (6)

Country Link
US (1) US5049543A (de)
EP (1) EP0336505B1 (de)
JP (1) JPH01302875A (de)
KR (1) KR890016625A (de)
DE (1) DE68911973T2 (de)
NL (1) NL8800857A (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63314850A (ja) * 1987-06-18 1988-12-22 Fujitsu Ltd 半導体装置
US5256897A (en) * 1988-11-28 1993-10-26 Hitachi, Ltd. Oxide superconducting device
US5274249A (en) * 1991-12-20 1993-12-28 University Of Maryland Superconducting field effect devices with thin channel layer
US5418214A (en) * 1992-07-17 1995-05-23 Northwestern University Cuprate-titanate superconductor and method for making
US5356474A (en) * 1992-11-27 1994-10-18 General Electric Company Apparatus and method for making aligned Hi-Tc tape superconductors
US5356833A (en) * 1993-04-05 1994-10-18 Motorola, Inc. Process for forming an intermetallic member on a semiconductor substrate
US6081182A (en) * 1996-11-22 2000-06-27 Matsushita Electric Industrial Co., Ltd. Temperature sensor element and temperature sensor including the same
US6642567B1 (en) * 2000-08-31 2003-11-04 Micron Technology, Inc. Devices containing zirconium-platinum-containing materials and methods for preparing such materials and devices
US8641839B2 (en) * 2007-02-13 2014-02-04 Yale University Method for imprinting and erasing amorphous metal alloys
US7951708B2 (en) * 2009-06-03 2011-05-31 International Business Machines Corporation Copper interconnect structure with amorphous tantalum iridium diffusion barrier
US9741918B2 (en) 2013-10-07 2017-08-22 Hypres, Inc. Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55164860U (de) * 1979-05-16 1980-11-27
JPS58110084A (ja) * 1981-12-24 1983-06-30 Mitsubishi Electric Corp ジヨセフソン素子
US4432134A (en) * 1982-05-10 1984-02-21 Rockwell International Corporation Process for in-situ formation of niobium-insulator-niobium Josephson tunnel junction devices
JPS603797B2 (ja) * 1982-05-29 1985-01-30 工業技術院長 ジヨセフソン・トンネル接合素子
US4470190A (en) * 1982-11-29 1984-09-11 At&T Bell Laboratories Josephson device fabrication method
JPS58212186A (ja) * 1983-05-06 1983-12-09 Hitachi Ltd ジヨセフソン接合装置
JPS60148178A (ja) * 1984-01-12 1985-08-05 Nippon Telegr & Teleph Corp <Ntt> トンネル形ジヨセフソン接合素子及びその製法
JPS616882A (ja) * 1984-06-21 1986-01-13 Agency Of Ind Science & Technol 超電導集積回路の端子電極とその製造方法
JPH0634414B2 (ja) * 1986-01-14 1994-05-02 富士通株式会社 超伝導デバイス
DE3810494C2 (de) * 1987-03-27 1998-08-20 Hitachi Ltd Integrierte Halbleiterschaltungseinrichtung mit supraleitender Schicht

Also Published As

Publication number Publication date
NL8800857A (nl) 1989-11-01
US5049543A (en) 1991-09-17
DE68911973T2 (de) 1994-07-07
EP0336505B1 (de) 1994-01-05
JPH01302875A (ja) 1989-12-06
EP0336505A1 (de) 1989-10-11
KR890016625A (ko) 1989-11-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee