DE69132271D1 - Gerät um befehle für einen prozessor mit parallelbefehlen vorzubereiten und gerät mit einem verfahren um mitten in einem verbundbefehl zu verzweigen - Google Patents

Gerät um befehle für einen prozessor mit parallelbefehlen vorzubereiten und gerät mit einem verfahren um mitten in einem verbundbefehl zu verzweigen

Info

Publication number
DE69132271D1
DE69132271D1 DE69132271T DE69132271T DE69132271D1 DE 69132271 D1 DE69132271 D1 DE 69132271D1 DE 69132271 T DE69132271 T DE 69132271T DE 69132271 T DE69132271 T DE 69132271T DE 69132271 D1 DE69132271 D1 DE 69132271D1
Authority
DE
Germany
Prior art keywords
instruction
compound
processor
execution
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132271T
Other languages
English (en)
Other versions
DE69132271T2 (de
Inventor
Stamatis Vassiliadis
Bartholomew Blaner
Leo Jeremiah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/543,458 external-priority patent/US5197135A/en
Priority claimed from US07/642,011 external-priority patent/US5295249A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69132271D1 publication Critical patent/DE69132271D1/de
Publication of DE69132271T2 publication Critical patent/DE69132271T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
DE69132271T 1990-05-04 1991-03-29 Gerät um befehle für einen prozessor mit parallelbefehlen vorzubereiten und gerät mit einem verfahren um mitten in einem verbundbefehl zu verzweigen Expired - Fee Related DE69132271T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US51938490A 1990-05-04 1990-05-04
US51938290A 1990-05-04 1990-05-04
US07/543,458 US5197135A (en) 1990-06-26 1990-06-26 Memory management for scalable compound instruction set machines with in-memory compounding
US07/642,011 US5295249A (en) 1990-05-04 1991-01-15 Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
PCT/US1991/002037 WO1991017496A1 (en) 1990-05-04 1991-03-29 System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction

Publications (2)

Publication Number Publication Date
DE69132271D1 true DE69132271D1 (de) 2000-08-03
DE69132271T2 DE69132271T2 (de) 2000-12-21

Family

ID=46201961

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132271T Expired - Fee Related DE69132271T2 (de) 1990-05-04 1991-03-29 Gerät um befehle für einen prozessor mit parallelbefehlen vorzubereiten und gerät mit einem verfahren um mitten in einem verbundbefehl zu verzweigen

Country Status (7)

Country Link
EP (2) EP0481031A4 (de)
JP (2) JPH0680489B2 (de)
AT (1) ATE194236T1 (de)
DE (1) DE69132271T2 (de)
HU (1) HU216990B (de)
PL (1) PL166513B1 (de)
WO (2) WO1991017496A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0728639A (ja) * 1993-07-13 1995-01-31 Nec Corp マイクロプロセッサ
US5619665A (en) * 1995-04-13 1997-04-08 Intrnational Business Machines Corporation Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture
US7840717B2 (en) * 2008-02-14 2010-11-23 International Business Machines Corporation Processing a variable length device command word at a control unit in an I/O processing system
US11204768B2 (en) 2019-11-06 2021-12-21 Onnivation Llc Instruction length based parallel instruction demarcator
US11334491B1 (en) * 2020-11-18 2022-05-17 Centaur Technology, Inc. Side cache array for greater fetch bandwidth

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
US4439828A (en) * 1981-07-27 1984-03-27 International Business Machines Corp. Instruction substitution mechanism in an instruction handling unit of a data processing system
US4586127A (en) * 1982-11-03 1986-04-29 Burroughs Corp. Multiple control stores for a pipelined microcontroller
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
US4574348A (en) * 1983-06-01 1986-03-04 The Boeing Company High speed digital signal processor architecture
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
JPS60101644A (ja) * 1983-11-07 1985-06-05 Masahiro Sowa ノイマン型コンピュータプログラムを実行するコントロールフローコンピュータ
JPH0769818B2 (ja) * 1984-10-31 1995-07-31 株式会社日立製作所 デ−タ処理装置
US4755966A (en) * 1985-06-28 1988-07-05 Hewlett-Packard Company Bidirectional branch prediction and optimization
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置

Also Published As

Publication number Publication date
EP0545927A1 (de) 1993-06-16
HU9200024D0 (en) 1992-03-30
HUT60048A (en) 1992-07-28
WO1991017495A1 (en) 1991-11-14
DE69132271T2 (de) 2000-12-21
EP0481031A4 (en) 1993-01-27
JPH04505823A (ja) 1992-10-08
PL166513B1 (pl) 1995-05-31
EP0481031A1 (de) 1992-04-22
ATE194236T1 (de) 2000-07-15
EP0545927B1 (de) 2000-06-28
HU216990B (hu) 1999-10-28
PL293182A1 (en) 1992-10-19
WO1991017496A1 (en) 1991-11-14
JPH0680489B2 (ja) 1994-10-12
JPH0679273B2 (ja) 1994-10-05
JPH04506878A (ja) 1992-11-26
EP0545927A4 (de) 1993-04-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee