EP0481031A1 - System um befehlssätze zusammenzusetzen zur befehlssatz- und datenstromverarbeitung für einen prozessor mit verschiedenen attributen - Google Patents
System um befehlssätze zusammenzusetzen zur befehlssatz- und datenstromverarbeitung für einen prozessor mit verschiedenen attributenInfo
- Publication number
- EP0481031A1 EP0481031A1 EP91907170A EP91907170A EP0481031A1 EP 0481031 A1 EP0481031 A1 EP 0481031A1 EP 91907170 A EP91907170 A EP 91907170A EP 91907170 A EP91907170 A EP 91907170A EP 0481031 A1 EP0481031 A1 EP 0481031A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- instruction
- instructions
- compounding
- compound
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000013329 compounding Methods 0.000 title claims abstract description 257
- 150000001875 compounds Chemical class 0.000 claims abstract description 262
- 238000000034 method Methods 0.000 claims description 62
- 230000015654 memory Effects 0.000 claims description 36
- 238000012545 processing Methods 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 28
- 239000002131 composite material Substances 0.000 claims description 10
- 238000005457 optimization Methods 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 35
- 230000007246 mechanism Effects 0.000 description 16
- 230000006870 function Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 230000006872 improvement Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 230000018109 developmental process Effects 0.000 description 5
- 230000001419 dependent effect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000008520 organization Effects 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 3
- 239000000872 buffer Substances 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000012536 storage buffer Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
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- 230000000717 retained effect Effects 0.000 description 1
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- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Definitions
- halfwords which exist in an instruction are initialized to indicate that the halfword is not an initial compound instruction. Best pairs are picked for compounding according to said compounding rules.
- the system employs a technique for choosing instructions for com ⁇ pounding includes instructions which cannot be compounded and certain instructions which are examined are tagged to indicate that a specific instruc ⁇ tion is not an initial instruction, and in the event that the initial instruction of the set being examined is not an appropriate as an initial compound instruc ⁇ tion marking that instruction that it is not an initial instruction.
- the system proceeds to examine a subsequent group of instructions which includes the next sequential instruction in the group which had just been examined.
- FIGURE 14 illustrates the logical and hardware implementation of the worst case compounder.
- FIGURE 16 illustrates a compounding example of the worst case with four instructions per group.
- the tag bits which are generated in memory, are "1" for the first compounded instruction and "zero" for the second compounded instruction. However, if the first and second instructions cannot be compounded, the tag bit for the first instruction is "zero" and the second and third instructions are then considered for compounding.
- the unique technique of this invention works equally well with either fixed or variable length instructions since once the start of an instruction is known (or pre- sumed), the length can always be found in one way or another somewhere in the instructions.
- the length is encoded in the opcode, while in other systems the length maybe encoded in the operands.
- the illus ⁇ trated examples of opcodes illustrated may be either fixed or of variable length.
- This storage mechanism includes a first storage mechanism for storing instructions and data to be processed in the form of a series of base instructions for a scalar machine.
- This storage mechanism is identified as higher-level storage 136.
- This storage (also "main memory”) is a large capacity lower speed storage mech ⁇ anism and may be, for example, a large capacity system storage unit or the lower portion of a comprehensive hierarchical storage system.
- the computer system of FIGURE 4-B also includes an instruction fetch and issue mechanism coupled to compound instruction cache 138 for supplying adjacent instructions stored therein to different ones of the functional instruc ⁇ tion processing units 139-141 when the instruction tag bits indicate that they may be processed in parallel.
- This mechanism also provides single instructions to individual functional units when their tag bits indicate parallel execution is not possible and they must be processed singly.
- This mech ⁇ anism is represented by instruction fetch and issue unit 142.
- Fetch and issue unit 142 fetches instructions form the cache 138 and examines the tag bits and instruction operation code (opcode) fields, performing a decode function, and based upon such examinations sends the instruction under consideration to the appropriate ones of the functional units 138- 141. .
- the bits T of FIGURE 9 are defined to indicate a specific meaning.
- the t 0 bit will mark the beginning of an instruction, as illustrated below. In all cases a 0 shall mean not asserted. In all cases it is preferred to have the compound instruction fetched with a certainty. Accordingly, the number of bits chosen for fetching is the maximum of number of bits which may be contained and could be executed with an instruction of the maximum instruction length of the target machine which is executing the parallel com ⁇ pounded instructions. Thus the fetching system provides for maximum length fetching.
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Devices For Executing Special Programs (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US51938490A | 1990-05-04 | 1990-05-04 | |
US51938290A | 1990-05-04 | 1990-05-04 | |
US519384 | 1990-05-04 | ||
US519382 | 1990-05-04 | ||
US543458 | 1990-06-26 | ||
US07/543,458 US5197135A (en) | 1990-06-26 | 1990-06-26 | Memory management for scalable compound instruction set machines with in-memory compounding |
US07/642,011 US5295249A (en) | 1990-05-04 | 1991-01-15 | Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel |
US642011 | 1991-01-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0481031A1 true EP0481031A1 (de) | 1992-04-22 |
EP0481031A4 EP0481031A4 (en) | 1993-01-27 |
Family
ID=46201961
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91908085A Expired - Lifetime EP0545927B1 (de) | 1990-05-04 | 1991-03-29 | Gerät um befehle für einen prozessor mit parallelbefehlen vorzubereiten und gerät mit einem verfahren um mitten in einem verbundbefehl zu verzweigen |
EP19910907170 Withdrawn EP0481031A4 (en) | 1990-05-04 | 1991-03-29 | System for compounding instructions for handling instruction and data stream for processor with different attributes |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91908085A Expired - Lifetime EP0545927B1 (de) | 1990-05-04 | 1991-03-29 | Gerät um befehle für einen prozessor mit parallelbefehlen vorzubereiten und gerät mit einem verfahren um mitten in einem verbundbefehl zu verzweigen |
Country Status (7)
Country | Link |
---|---|
EP (2) | EP0545927B1 (de) |
JP (2) | JPH0679273B2 (de) |
AT (1) | ATE194236T1 (de) |
DE (1) | DE69132271T2 (de) |
HU (1) | HU216990B (de) |
PL (1) | PL166513B1 (de) |
WO (2) | WO1991017496A1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0728639A (ja) * | 1993-07-13 | 1995-01-31 | Nec Corp | マイクロプロセッサ |
US5619665A (en) * | 1995-04-13 | 1997-04-08 | Intrnational Business Machines Corporation | Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture |
US7840717B2 (en) * | 2008-02-14 | 2010-11-23 | International Business Machines Corporation | Processing a variable length device command word at a control unit in an I/O processing system |
US11204768B2 (en) | 2019-11-06 | 2021-12-21 | Onnivation Llc | Instruction length based parallel instruction demarcator |
US11334491B1 (en) * | 2020-11-18 | 2022-05-17 | Centaur Technology, Inc. | Side cache array for greater fetch bandwidth |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4295193A (en) * | 1979-06-29 | 1981-10-13 | International Business Machines Corporation | Machine for multiple instruction execution |
EP0071028A2 (de) * | 1981-07-27 | 1983-02-09 | International Business Machines Corporation | Instruktionsverarbeitungseinheit in einer Datenverarbeitungsanlage mit Instruktionssubstitution und Arbeitsverfahren |
US4594655A (en) * | 1983-03-14 | 1986-06-10 | International Business Machines Corporation | (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions |
EP0239081A2 (de) * | 1986-03-26 | 1987-09-30 | Hitachi, Ltd. | Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen |
US4780820A (en) * | 1983-11-07 | 1988-10-25 | Masahiro Sowa | Control flow computer using mode and node driving registers for dynamically switching between parallel processing and emulation of von neuman processors |
US4847755A (en) * | 1985-10-31 | 1989-07-11 | Mcc Development, Ltd. | Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4586127A (en) * | 1982-11-03 | 1986-04-29 | Burroughs Corp. | Multiple control stores for a pipelined microcontroller |
US4574348A (en) * | 1983-06-01 | 1986-03-04 | The Boeing Company | High speed digital signal processor architecture |
US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
JPH0769818B2 (ja) * | 1984-10-31 | 1995-07-31 | 株式会社日立製作所 | デ−タ処理装置 |
US4755966A (en) * | 1985-06-28 | 1988-07-05 | Hewlett-Packard Company | Bidirectional branch prediction and optimization |
JPS63131230A (ja) * | 1986-11-21 | 1988-06-03 | Hitachi Ltd | 情報処理装置 |
-
1991
- 1991-03-29 DE DE69132271T patent/DE69132271T2/de not_active Expired - Fee Related
- 1991-03-29 JP JP3507600A patent/JPH0679273B2/ja not_active Expired - Fee Related
- 1991-03-29 WO PCT/US1991/002037 patent/WO1991017496A1/en active IP Right Grant
- 1991-03-29 HU HU9200024A patent/HU216990B/hu unknown
- 1991-03-29 JP JP3507370A patent/JPH0680489B2/ja not_active Expired - Lifetime
- 1991-03-29 AT AT91908085T patent/ATE194236T1/de not_active IP Right Cessation
- 1991-03-29 EP EP91908085A patent/EP0545927B1/de not_active Expired - Lifetime
- 1991-03-29 WO PCT/US1991/002040 patent/WO1991017495A1/en not_active Application Discontinuation
- 1991-03-29 EP EP19910907170 patent/EP0481031A4/en not_active Withdrawn
- 1991-03-29 PL PL91293182A patent/PL166513B1/pl not_active IP Right Cessation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4295193A (en) * | 1979-06-29 | 1981-10-13 | International Business Machines Corporation | Machine for multiple instruction execution |
EP0071028A2 (de) * | 1981-07-27 | 1983-02-09 | International Business Machines Corporation | Instruktionsverarbeitungseinheit in einer Datenverarbeitungsanlage mit Instruktionssubstitution und Arbeitsverfahren |
US4594655A (en) * | 1983-03-14 | 1986-06-10 | International Business Machines Corporation | (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions |
US4780820A (en) * | 1983-11-07 | 1988-10-25 | Masahiro Sowa | Control flow computer using mode and node driving registers for dynamically switching between parallel processing and emulation of von neuman processors |
US4847755A (en) * | 1985-10-31 | 1989-07-11 | Mcc Development, Ltd. | Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies |
EP0239081A2 (de) * | 1986-03-26 | 1987-09-30 | Hitachi, Ltd. | Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen |
Non-Patent Citations (1)
Title |
---|
See also references of WO9117495A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPH0680489B2 (ja) | 1994-10-12 |
EP0545927A1 (de) | 1993-06-16 |
HU9200024D0 (en) | 1992-03-30 |
HU216990B (hu) | 1999-10-28 |
PL293182A1 (en) | 1992-10-19 |
ATE194236T1 (de) | 2000-07-15 |
JPH04505823A (ja) | 1992-10-08 |
HUT60048A (en) | 1992-07-28 |
EP0481031A4 (en) | 1993-01-27 |
JPH04506878A (ja) | 1992-11-26 |
WO1991017495A1 (en) | 1991-11-14 |
DE69132271T2 (de) | 2000-12-21 |
PL166513B1 (pl) | 1995-05-31 |
DE69132271D1 (de) | 2000-08-03 |
EP0545927B1 (de) | 2000-06-28 |
EP0545927A4 (de) | 1993-04-26 |
WO1991017496A1 (en) | 1991-11-14 |
JPH0679273B2 (ja) | 1994-10-05 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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17P | Request for examination filed |
Effective date: 19911202 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB |
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A4 | Supplementary search report drawn up and despatched |
Effective date: 19921207 |
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AK | Designated contracting states |
Kind code of ref document: A4 Designated state(s): DE FR GB |
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17Q | First examination report despatched |
Effective date: 19970403 |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 19970814 |