DE69129767D1 - Vielfachsegmentbus und Betriebsverfahren - Google Patents

Vielfachsegmentbus und Betriebsverfahren

Info

Publication number
DE69129767D1
DE69129767D1 DE69129767T DE69129767T DE69129767D1 DE 69129767 D1 DE69129767 D1 DE 69129767D1 DE 69129767 T DE69129767 T DE 69129767T DE 69129767 T DE69129767 T DE 69129767T DE 69129767 D1 DE69129767 D1 DE 69129767D1
Authority
DE
Germany
Prior art keywords
operating procedures
segment bus
segment
bus
procedures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69129767T
Other languages
English (en)
Other versions
DE69129767T2 (de
Inventor
Richard H Bruce
Jean Gastinel
William F Gunning
Michael Overton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Publication of DE69129767D1 publication Critical patent/DE69129767D1/de
Application granted granted Critical
Publication of DE69129767T2 publication Critical patent/DE69129767T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)
DE69129767T 1990-03-06 1991-03-06 Vielfachsegmentbus und Betriebsverfahren Expired - Lifetime DE69129767T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49011390A 1990-03-06 1990-03-06

Publications (2)

Publication Number Publication Date
DE69129767D1 true DE69129767D1 (de) 1998-08-20
DE69129767T2 DE69129767T2 (de) 1999-02-04

Family

ID=23946685

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69129767T Expired - Lifetime DE69129767T2 (de) 1990-03-06 1991-03-06 Vielfachsegmentbus und Betriebsverfahren

Country Status (4)

Country Link
US (3) US5685004A (de)
EP (1) EP0446039B1 (de)
JP (1) JP3118266B2 (de)
DE (1) DE69129767T2 (de)

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US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
EP0578386B1 (de) * 1992-06-17 1998-10-21 Texas Instruments Incorporated Hierarchisches Verbindungsverfahren, -gerät und -protokoll
EP0752167A4 (de) * 1994-03-21 1998-09-02 Intel Corp Verfahren und einrichtung für integrierbare spannungsregelungsschaltungsanordnung
US5734840A (en) * 1995-08-18 1998-03-31 International Business Machines Corporation PCI and expansion bus riser card
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US6493407B1 (en) * 1997-05-27 2002-12-10 Fusion Micromedia Corporation Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method
EP0892352B1 (de) * 1997-07-18 2005-04-13 Bull S.A. Rechnersystem mit einem geteilten strukturierten Bus
US6043558A (en) * 1997-09-12 2000-03-28 Micron Technology, Inc. IC packages including separated signal and power supply edge connections, systems and devices including such packages, and methods of connecting such packages
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
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JP2003505753A (ja) 1999-06-10 2003-02-12 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング セル構造におけるシーケンス分割方法
WO2001025941A1 (en) 1999-10-06 2001-04-12 Cradle Technologies Multiprocessor computer systems with command fifo buffer at each target device
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
JP2002026130A (ja) * 2000-07-06 2002-01-25 Nec Microsystems Ltd 半導体集積回路及びｉ／ｏブロック配置方法
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6934785B2 (en) * 2000-12-22 2005-08-23 Micron Technology, Inc. High speed interface with looped bus
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9411532B2 (en) 2001-09-07 2016-08-09 Pact Xpp Technologies Ag Methods and systems for transferring data between a processing device and external devices
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9436631B2 (en) * 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US6882082B2 (en) * 2001-03-13 2005-04-19 Micron Technology, Inc. Memory repeater
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US6640331B2 (en) * 2001-11-29 2003-10-28 Sun Microsystems, Inc. Decoupling capacitor assignment technique with respect to leakage power
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US20070011433A1 (en) * 2003-04-04 2007-01-11 Martin Vorbach Method and device for data processing
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
US6996652B1 (en) * 2002-09-19 2006-02-07 Inapac Technology, Inc. High-speed segmented data bus architecture
KR20050095599A (ko) * 2002-12-30 2005-09-29 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 클러스터된 ｉｌｐ 프로세서
KR100631673B1 (ko) * 2003-12-30 2006-10-09 엘지전자 주식회사 이동통신용 고주파 모듈 구조
JP2006245336A (ja) * 2005-03-03 2006-09-14 Koito Mfg Co Ltd 発光装置
US20070015464A1 (en) * 2005-07-12 2007-01-18 Mark Disalvo Interactive venue system
GB2464703A (en) * 2008-10-22 2010-04-28 Advanced Risc Mach Ltd An array of interconnected processors executing a cycle-based program

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FR2432175A1 (fr) * 1978-07-27 1980-02-22 Cii Honeywell Bull Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procede
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US4562535A (en) * 1982-04-05 1985-12-31 Texas Instruments Incorporated Self-configuring digital processor system with global system
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FR2605768B1 (fr) * 1986-10-23 1989-05-05 Bull Sa Dispositif de commande de bus constitue par plusieurs segments isolables
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US4899307A (en) * 1987-04-10 1990-02-06 Tandem Computers Incorporated Stack with unary encoded stack pointer
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US4827476A (en) * 1987-04-16 1989-05-02 Tandem Computers Incorporated Scan test apparatus for digital systems having dynamic random access memory
US4933846A (en) * 1987-04-24 1990-06-12 Network Systems Corporation Network communications adapter with dual interleaved memory banks servicing multiple processors
DE3782819D1 (de) * 1987-06-02 1993-01-07 Itt Ind Gmbh Deutsche Steuerprozessor.
US4933838A (en) * 1987-06-03 1990-06-12 The Boeing Company Segmentable parallel bus for multiprocessor computer systems
US4845663A (en) * 1987-09-03 1989-07-04 Minnesota Mining And Manufacturing Company Image processor with free flow pipeline bus
US4933845A (en) * 1987-09-04 1990-06-12 Digital Equipment Corporation Reconfigurable bus
US4974153A (en) * 1987-09-04 1990-11-27 Digital Equipment Corporation Repeater interlock scheme for transactions between two buses including transaction and interlock buffers
US4965723A (en) * 1987-10-23 1990-10-23 Digital Equipment Corporation Bus data path control scheme
JP2944084B2 (ja) * 1988-04-14 1999-08-30 日本電気株式会社 シリアル入出力回路
US5107507A (en) * 1988-05-26 1992-04-21 International Business Machines Bidirectional buffer with latch and parity capability
JPH01320564A (ja) * 1988-06-23 1989-12-26 Hitachi Ltd 並列処理装置
US5119483A (en) * 1988-07-20 1992-06-02 Digital Equipment Corporation Application of state silos for recovery from memory management exceptions
US5173864A (en) * 1988-08-20 1992-12-22 Kabushiki Kaisha Toshiba Standard cell and standard-cell-type integrated circuit
US5050066A (en) * 1988-10-14 1991-09-17 Intel Corporation Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus
EP0365322A3 (de) * 1988-10-19 1991-11-27 Hewlett-Packard Company Verfahren und Vorrichtung zur Ausnahmenbehandlung in Fliessbandprozessoren mit unterschiedlicher Befehlspipelinetiefe
US5006982A (en) * 1988-10-21 1991-04-09 Siemens Ak. Method of increasing the bandwidth of a packet bus by reordering reply packets
US5097410A (en) * 1988-12-30 1992-03-17 International Business Machines Corporation Multimode data system for transferring control and data information in an i/o subsystem
GB2234613B (en) * 1989-08-03 1993-07-07 Sun Microsystems Inc Method and apparatus for switching context of state elements in a microprocessor
US5408146A (en) * 1992-01-31 1995-04-18 Lsi Logic Corporation High performance backplane driver circuit
US5491428A (en) * 1993-12-20 1996-02-13 Hitachi Microsystems, Inc. Bus-isolating pre-charge buffer

Also Published As

Publication number Publication date
EP0446039B1 (de) 1998-07-15
US5685004A (en) 1997-11-04
US5978880A (en) 1999-11-02
US5632029A (en) 1997-05-20
EP0446039A2 (de) 1991-09-11
EP0446039A3 (en) 1991-12-27
JP3118266B2 (ja) 2000-12-18
DE69129767T2 (de) 1999-02-04
JPH06266659A (ja) 1994-09-22

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